參數(shù)資料
型號： M37753FFCHP
廠商： Mitsubishi Electric Corporation
英文描述： SINGLE CHIP 16 BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
中文描述： 單片微機(jī)16位CMOS閃存版
文件頁數(shù)： 41/67頁
文件大?。?/td> 525K
代理商： M37753FFCHP
41
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37753FFCFP
M37753FFCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
t
c(TB)
t
w(TBH)
t
w(TBL)
t
c(TB)
t
w(TBH)
t
w(TBL)
Timer B input
(Count input in event counter mode)
Symbol
TBi
IN
input cycle time (one edge count)
TBi
IN
input high-level pulse width (one edge count)
TBi
IN
input low-level pulse width (one edge count)
TBi
IN
input cycle time (both edge count)
TBi
IN
input high-level pulse width (both edge count)
TBi
IN
input low-level pulse width (both edge count)
Parameter
Limits
Min.
80
40
40
160
80
80
Max.
ns
ns
ns
ns
ns
ns
Unit
Limits
Symbol
Parameter
Min.
Max.
Unit
16
×
10
9
f(X
IN
)
8
×
10
9
f(X
IN
)
8
×
10
9
f(X
IN
)
4
×
10
9
f(X
IN
)
8
×
10
9
f(X
IN
)
4
×
10
9
f(X
IN
)
(400)
(320)
(200)
(160)
(200)
(160)
f(X
IN
)
≤
40 MHz
f(X
IN
)
≤
25 MHz
f(X
IN
)
≤
40 MHz
f(X
IN
)
≤
25 MHz
f(X
IN
)
≤
40 MHz
f(X
IN
)
≤
25 MHz
t
c(TB)
t
w(TBH)
t
w(TBL)
TBi
IN
input cycle time
TBi
IN
input high-level pulse width
TBi
IN
input low-level pulse width
ns
ns
ns
ns
ns
ns
Timer B input
(Pulse period measurement mode)
Note : The TBi
IN
input cycle time requires 4 or more cycles of count source. The TBi
IN
input high-level pulse width and the TBi
IN
input low-level pulse width
respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(X
IN
)/4 in high-speed running
(f(X
IN
)
≤
40 MHz) and when the count source is f(X
IN
)/2 in low-speed running (f(X
IN
)
≤
25 MHz). At this time, the clock source select bit is “0.”
Limits
Symbol
Parameter
Min.
Max.
Unit
16
×
10
9
f(X
IN
)
8
×
10
9
f(X
IN
)
8
×
10
9
f(X
IN
)
4
×
10
9
f(X
IN
)
8
×
10
9
f(X
IN
)
4
×
10
9
f(X
IN
)
(400)
(320)
(200)
(160)
(200)
(160)
f(X
IN
)
≤
40 MHz
f(X
IN
)
≤
25 MHz
f(X
IN
)
≤
40 MHz
f(X
IN
)
≤
25 MHz
f(X
IN
)
≤
40 MHz
f(X
IN
)
≤
25 MHz
t
c(TB)
t
w(TBH)
t
w(TBL)
TBi
IN
input cycle time
TBi
IN
input high-level pulse width
TBi
IN
input low-level pulse width
ns
ns
ns
ns
ns
ns
Timer B input
(Pulse width measurement mode)
Note : The TBi
IN
input cycle time requires 4 or more cycles of count source. The TBi
IN
input high-level pulse width and the TBi
IN
input low-level pulse width
respectively require 2 or more cycles of the count source. The limits in the table are the values when the count source is f(X
IN
)/4 in high-speed running
(f(X
IN
)
≤
40 MHz) and when the count source is f(X
IN
)/2 in low-speed running (f(X
IN
)
≤
25 MHz). At this time, the clock source select bit is “0.”
t
c(AD)
t
w(ADL)
Symbol
AD
TRG
input cycle time (minimum allowable trigger)
AD
TRG
input low-level pulse width
Parameter
Min.
1000
125
Limits
Max.
ns
ns
Unit
A-D trigger input
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