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參數(shù)資料
| 型號： | M37753FFCHP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE CHIP 16 BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION |
| 中文描述： | 單片微機16位CMOS閃存版 |
| 文件頁數(shù)： | 28/67頁 |
| 文件大小： | 525K |
| 代理商： | M37753FFCHP |
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28
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37753FFCFP
M37753FFCHP
SHINGLE-CHIP 16-BIT CMOS MICROCOMPUTER FLASH MEMORY VERSION
Program command
Input command code 40
16
in the first transfer. Proceed and input the
low-order 8 bits and the high-order 8 bits of the address and then
program data. Programming is initiated at the last rising edge of the
serial clock during program data transfer. The BUSY pin is driven
high during program operation. Programming is completed within 10
μ
s as measured by the built-in timer, and the BUSY pin is pulled low.
Note :
A programming operation is not completed by executing the
program command once. Always be sure to execute a pro-
gram verify command after executing the program command.
In the case of failure in the verification, the user must repeat-
edly execute the program command until the pass in the veri-
fication. Refer to Figure 12 for the programming flowchart.
Program verify command
Input command code C0
16
in the first transfer. Proceed and drive the
OE pin low. When this is done, the M37753FFCFP and the
M37753FFCHP verify-read the programmed address’s contents,
and then latch it into the internal data latch. When the OE pin is re-
leased back high and serial clock is input to the SCLK pin, the verify
data that has been latched into the data latch is serially output from
the SDA pin.
Fig. 18 Timings during program verify
Fig. 17 Timings during programming
SCLK
BUSY
OE
SDA
t
CH
A
0
0 0 0 0 0 0 1 0
Command code input (40
16
)
A
7
A
8
A
15
D
0
D
7
t
CH
t
CH
t
PC
Program address input (L)
Program address input (H)
Program data input
t
WP
Program
SCLK
BUSY
OE
SDA
D
0
D
7
t
CRPV
Command code input (C0
16
)
Verify data output
t
WR
Verify read
t
RC
Note:
When outputting the verify data, the SDA pin is switched for output at the first falling edge of SCLK. The SDA pin is placed
in the floating state during the period of th
(C-E)
after the last rising edge of SCLK (at the 8th bit).
0 0 0 0 0 0 1 1
“L”
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