參數(shù)資料
型號(hào)： M37736EHLXXXHP
廠商： Mitsubishi Electric Corporation
英文描述： PROM VERSION OF M37736MHLXXXHP(MICROCOMPUTERS)
中文描述： PROM的版本M37736MHLXXXHP（微型）
文件頁數(shù)： 55/96頁
文件大?。?/td> 1328K
代理商： M37736EHLXXXHP
55
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Single-chip mode
_
E
E, RDE, WEL, WEH
_
_ ___ ___ ___
are output when the
internal/external memory area is accessed.
E, RDE, WEL, WEH
are output only when
the external memory area is accessed.
“L” is output after WIT/STP instruction is
executed.
Standby state selection bit (bit 0 of port
function control register) must be set to
“1”.
“H”or “L” is output. (Output the content of
P4
2
latch.)
Port P4
2
direction register must be set to
“1”.
(3) Microprocessor mode [10]
Microprocessor mode is entered by connecting the CNVss pin to Vcc
and starting from reset. It can also be entered by programming the
processor mode bits to “10” after connecting the CNVss pin to Vss
and starting from reset. This mode (for both the external bus mode A
and the external bus mode B) is similar to the memory expansion
mode except that internal ROM is disabled and an external memory
is required, and clock
of bit 7 of the processor mode register 0.
As shown in Table 7,
output disable selection bit “1”. In this case, write “1” to the port P4
2
direction register.
1
from port P4
2
is always output independently
1
output can also be stopped with the signal
(4) Evaluation chip mode [11]
Evaluation chip mode can be selected at the external bus mode A
only.
Evaluation chip mode is entered by applying voltage twice the V
CC
voltage to the CNV
SS
pin. This mode is normally used for evaluation
tools.
_
The functions of
E
, ports P0 and P3 are the same as those in memory
expansion mode.
Port P1 functions as an address output pin while
E
is “H” and as data
I/O pin of odd addresses while
E
is “L” regardless of the BYTE pin
level.
Port P2 function as an address output pin while
E
is “H” and as data
I/O pin of even addresses while
E
is “L” when the BYTE pin level is
“L”.
When the BYTE pin level is “H” or 2·V
CC
, port P2 functions as an
address output pin while
E
is “H” and as data I/O pin of even and odd
addresses while
E
is “L”.
Port P4 and its data direction register which are located at address
0A
16
and 0C
16
are treated differently in evaluation chip mode. When
these addresses are accessed, the data bus width is treated as 16
bits regardless of the BYTE pin level, and the access cycle is treated
as internal memory regardless of the wait bit.
_
_
When a voltage twice the V
CC
voltage is applied to the BYTE pin, the
addresses corresponding to the internal ROM area are also treated
as 16-bit data bus.
The functions of ports P4
0
and P4
1
are the same as in memory
expansion mode.
Ports P4
2
to P4
6
become
respectively. Port P4
7
becomes the
DBC
input pin.
1
from port P4
2
is always output regardless of bit 7 of processor
mode register 0.
Signal MX normally contains the contents of flag m, however, the
contents of flag x is output when the CPU is using flag x.
QCL is the queue buffer clear signal. It becomes “H” when the
instruction queue buffer is cleared, for example, when a jump
instruction is executed.
VDA is the valid data address signal. It becomes “H” while the CPU
is reading data from data buffer or writing data to data buffer. It also
becomes “H” when the first byte of the instruction (operation code) is
read from the instruction queue buffer.
VPA is the valid program address signal. It becomes “H” while the
___
DBC
is the debug control signal and is used for debugging.
Table 9 shows the relationship between the CNVss pin input level
and the processor modes.
1
, MX, QCL, VDA, and VPA output pins
Table 9. Relationship between CNVss pin input levels and processor
modes
CNVss
Mode
Single-chip
Memory expansion
Microprocessor
( Evaluation chip)
Description
Single-chip mode upon
starting after reset. Each
mode can be selected by
changing the processor
mode bits by software.
Microprocessor mode upon
starting after reset.
Evaluation chip mode only.
Microprocessor
( Evaluation chip)
Evaluation chip
Vss
Vcc
2·Vcc
Table 7. Function of signal output disable selection bit CM
6
(bit 6 of oscillation circuit control register 0)
Function
CM
6
= “0”
CM
6
= “1”
Processor mode
Pin
After WIT/STP instruction is executed,
“H” is output.
Memory expansion mode,
Microprocessor mode
_ ___
E, RDE
Note.
Functions shown in Table 7 cannot be emulated in a debugger. For the oscillation circuit control register 0, refer to Figure 64.
For the port function control register, refer to Figure 11.
Note.
In the external bus mode B, the evaluation chip mode cannot
be selected.
Clock
output selection bit.
1
is output independent of
1
Microprocessor mode
1
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