參數(shù)資料
型號(hào)： M37736EHLXXXHP
廠商： Mitsubishi Electric Corporation
英文描述： PROM VERSION OF M37736MHLXXXHP(MICROCOMPUTERS)
中文描述： PROM的版本M37736MHLXXXHP（微型）
文件頁數(shù)： 40/96頁
文件大?。?/td> 1328K
代理商： M37736EHLXXXHP
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MITSUBISHI MICROCOMPUTERS
M37736MHBXXXGP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
40
Receive
Receive is enabled when bit 2 (RE
i
flag) of the UART
i
transmit/receive
control register 1 is set to “1”. As shown in Figure 48, the frequency
divider circuit at the receiving end begin to work when a start bit is
arrived and the data is received.
If
RTS
i
output is selected by setting bit 2 of the UART
i
transmit/receive
control register 0 to “1”, the
RTS
i
output is “H” when the RE
i
flag is “0”.
When the RE
i
flag changes to “1”, the
RTS
i
output goes “L” to indicate
receive ready and returns to “H” once receive has started. In other
words,
RTS
i
output can be used to determine externally whether the
receive register is ready to receive. (UART2 does not have the
RTS
output function.)
The entire transmission data bits are received when the start bit
passes the final bit of the receive register of the receive block shown
in Figure 38. At this point, the contents of the receive register is
transferred to the receive buffer register and the bit 3 of the UART
i
transmit/receive control register 1 (RI
i
flag) is set. In other words, the
RI
i
flag indicates that the receive buffer register contains data when it
is set. If
RTS
i
output is selected,
RTS
i
output goes “L” to indicate that
the register is ready to receive the next data.
The interrupt request bit of the UART
i
receive (transmit/receive in
UART2) interrupt control register is set when the RI
i
flag changes
from “0” to “1”.
The bit 4 (OER
i
flag) of the UART
i
transmission control register 1 is
set when the next data is transferred from the receive register to the
receive buffer register while the RI
i
flag is “1”. In other words when
an overrun error occurs. If the OER
i
flag is “1”, it indicates that the
next data has been transferred to the receive buffer register before
the contents of the receive butter register has been read.
Bit 5 (FER
i
flag) is set when the number of stop bits is less than
required (framing error).
Bit 6 (PER
i
flag) is set when a parity error occurs.
Bit 7 (SUM
i
flag) is set when either the OER
i
flag, FER
i
flag, or the
PER
i
flag is set. Therefore, the SUM
i
flag can be used to determine
whether there is an error.
The setting of the RI
i
flag, OER
i
flag, FER
i
flag, and the PER
i
flag is
performed while transferring the contents of the receive register to
the receive buffer register. The RI
i
, FER
i
, and PER
i
flags are cleared
when reading the low-order byte of the receive buffer register or when
writing “0” to the RE
i
flag or when setting to be a parallel port. The
OER
i
and SUM
i
flags are cleared when writing “0” to the RE
i
flag or
when the setting to be a parallel port.
Sleep mode
The sleep mode is used to communicate only between certain
microcomputers when multiple microcomputers are connected
through serial I/O.
The sleep mode is entered when bit 7 of the UART
i
transmit/receive
mode register is set to “1.”
UART2 does not have the sleep mode.
The operation of the sleep mode for an 8-bit asynchronous
communication is described below.
When sleep mode is selected, the contents of the receive register is
not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit
asynchronous communication and bit 8 if 9-bit asychronous
communication) of the received data is “0”. Also the RI
i
, OER
i
, FER
i
,
PER
i
, and the SUM
i
flag are unchanged. Therefore, the interrupt
request bit of the UART
i
receive interrupt control register is also
unchanged.
Normal receive operation takes place when bit 7 of the received data
is “1”.
The following is an example of how the sleep mode can be used.
The main microcomputer first sends data with bit 7 set to “1” and bits
0 to 6 set to the address of the subordinate microcomputer which
wants to communicate with. Then all subordinate microcomputers
receive the same data. Each subordinate microcomputer checks the
received data, clears the sleep function selection bit if bits 0 to 6 are
its own address and sets the sleep bit if not. Next the main
microcomputer sends data with bit 7 cleared. Then the microcomputer
with the sleep bit cleared will receive the data, but the microcomputer
with the sleep bit set will not. In this way, the main microcomputer is
able to communicate only with the designated microcomputer.
Fig. 48 Receive timing example when 8-bit asynchronous communication with no parity and 1 stop bit is selected
f
i
or f
EXT
D
0
RE
i
R
x
D
i
Receive
Clock
RI
i
RTS
i
Start bit
D
1
Stop bit
D
7
Start bit
Starting at the falling
edge of start bit
Check to be “L” level
Get data
相關(guān)PDF資料
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