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參數(shù)資料
| 型號(hào)： | M37641F8FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 82/140頁 |
| 文件大小： | 1694K |
| 代理商： | M37641F8FP |
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7641 Group
Rev.4.00
Aug 28, 2006
page 44 of 135
REJ03B0191-0400
USB Transmission
Endpoint 0 to Endpoint 4 have IN (transmit) FIFOs individually.
Each endpoint’s FIFO is configured in following way:
Endpoint 0: 16-byte
Endpoint 1: Mode 0: 512-byte
Mode 1: 1024-byte
Mode 2: 0-byte
Mode 3: 2048-byte
Mode 4: 768-byte
Mode 5: 880-byte
Endpoint 2: Mode 0: 32-byte
Mode 1: 128-byte
Endpoint 3: 16-byte
Endpoint 4: 16-byte
When Endpoint 1 or Endpoint 2 is used for data transmit, the IN
FIFO size can be selected. Endpoint 1 and Endpoint 2 have pro-
grammable IN-FIFOs size; 6 modes for Endpoint 1, and 2 modes
for Endpoint 2. Each mode can be selected by the USB endpoint
FIFO mode selection register (address 005F16).
When writing data to the USB Endpoint-x FIFO (addresses 006016
to 006416) in the SFR area, the internal write pointer for the IN
FIFO is automatically increased by 1. When the AUTO_SET bit is
“1” and if the stored data reaches to the max. packet value set in
USB Endpoint x IN max. packet size register (address 005B16),
the USB FCU sets the IN_PKT_RDY bit to “1”. When the
AUTO_SET bit is “0”, the IN_PKT_RDY bit will not be automati-
cally set to “1”; it must be set to “1” by software. (The AUTO_SET
bit function is not applicable to Endpoint 0.)
The USB FCU transmits the data when it receives the next IN to-
ken. The IN_PKT_RDY bit automatically goes to “0” when the data
transfer is complete.
qIsochronous transfer
Endpoints 1 to 4 can be used in isochronous transfer mode. When
using isochronous transfer mode, the ISO/TOGGLE_INIT bit must
be set to “1”. When ISO_UPDATE = “1” and the corresponding
endpoint’s ISO/TOGGLE_INIT bit = “1”, the USB FCU delays the
rise of the IN_PKT_RDY bit until the next SOF signal transmis-
sion. In this way, the USB FCU can synchronize a transmit data to
the SOF signal.
qInterrupt transfer mode
Endpoints 1 to 4 can be used in interrupt transfer mode. During a
regular interrupt transfer, an interrupt transaction is similar to the
bulk transfer. Therefore, there is no special setting required. When
IN-endpoint is used for a rate feedback interrupt transfer, INTPT
bit of the IN_CSR register must be set to “1”. The following steps
show how to configure the IN-endpoint for the rate feedback inter-
rupt transfer.
1. Set a value which is larger than 1/2 of the USB Endpoint-x FIFO
size to the USB Endpoint x IN max. package size register.
2. Set INTPT bit to “1”.
3. Flush the old data in the FIFO.
4. Store transmission data to the IN FIFO and set the
IN_PKT_RDY bit to “1”.
5. Repeat steps 3 and 4.
In a real application, the function-side always has transfer data
when the function sends an endpoint in a rate feedback interrupt.
Accordingly, the USB FCU never returns a NAK against the host
IN token for the rate feedback interrupt. The USB FCU always
transmits data in the FIFO in response to an IN token, regardless
of IN_PKT_RDY. However, this premises that there is always an
ACK response from Host PC after the 7641 Group has transmitted
data to IN token.
When MAXP size
≤ (a half of IN FIFO size), the IN FIFO can store
two packets (called double buffer). At this time, the IN FIFO sta-
tus can be checked by monitoring the IN_PKT_RDY bit and the
TX_NOT_EPT flag. The TX_NOT_EPT flag is a read-only flag
which shows the FIFO state. When IN_PKY_RDY = 0 and
TX_NOT_EPT = 0, IN FIFO is empty. When IN_PKY_RDY = 0 and
TX_NOT_EPT = 1, IN FIFO has one packet.
In double buffer mode, as long as the IN FIFO is not filled with
double packets, IN_PKT_RDY will not be set to “1”, even if it is set
to “1” by software, but TX_NOT_EPT flag will be set to “1”. In
single buffer mode, if MAXP > (a half of IN FIFO), this condition
never occurs.
When IN_PKT_RDY = “1” and TX_NOT_EPT = “1”, IN FIFO holds
two packets in double buffer mode and one packet in single
packet mode. In single packet mode, when the IN_PKT_RDY bit is
set to “1” by software, the TX_NOT_EPT flag is set to “1” as well.
During double buffer mode, if you want to load two packets se-
quentially, you must set the IN_PKT_RDY bit to “1” each time a
packet is loaded.
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相關(guān)代理商/技術(shù)參數(shù) |
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| M37641F8FP#U0 | 功能描述:IC 740 MCU FLASH 32K 80QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/7600 標(biāo)準(zhǔn)包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設(shè)備:POR，PWM，溫度傳感器，WDT 輸入/輸出數(shù):21 程序存儲(chǔ)器容量:40KB（20K x 16） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 6x12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323 |
| M37641F8HP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37641F8HP#U0 | 功能描述:IC 740 MCU FLASH 32K 80LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:740/7600 產(chǎn)品培訓(xùn)模塊:Graphics LCD System and PIC24 Interface Asynchronous Stimulus 標(biāo)準(zhǔn)包裝:27 系列:PIC® 24H 核心處理器:PIC 芯體尺寸:16-位 速度:40 MIP 連通性:I²C，SPI，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，POR，PWM，WDT 輸入/輸出數(shù):21 程序存儲(chǔ)器容量:12KB（4K x 24） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):3 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 10x10b/12b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 包裝:管件 產(chǎn)品目錄頁面:648 (CN2011-ZH PDF) 配用:AC164339-ND - MODULE SKT FOR PM3 28SOICDV164033-ND - KIT START EXPLORER 16 MPLAB ICD2 |
| M37641F8M8-XXXFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M37641F8-XXXFP | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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