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| 型號： | M37641F8FP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 12/140頁 |
| 文件大?。?/td> | 1694K |
| 代理商： | M37641F8FP |
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7641 Group
Rev.4.00
Aug 28, 2006
page 107 of 135
REJ03B0191-0400
Software Commands (CPU Rewrite Mode)
Table 26 lists the software commands.
After setting the CPU Rewrite Mode Select Bit of the flash memory
control register to “1”, execute a software command to specify an
erase or program operation.
Each software command is explained below.
qRead Array Command (FF16)
The read array mode is entered by writing the command code
“FF16” in the first bus cycle. When an address to be read is input in
one of the bus cycles that follow, the contents of the specified ad-
dress are read out at the data bus (DB0 to DB7).
The read array mode is retained intact until another command is
written.
qRead Status Register Command (7016)
The read status register mode is entered by writing the command
code “7016” in the first bus cycle. The contents of the status regis-
ter are read out at the data bus (DB0 to DB7) by a read in the
second bus cycle.
The status register is explained in the next section.
qClear Status Register Command (5016)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that opera-
tion has ended in an error. To use this command, write the
command code “5016” in the first bus cycle.
qProgram Command (4016)
Program operation starts when the command code “4016” is writ-
ten in the first bus cycle. Then, if the address and data to program
are written in the 2nd bus cycle, program operation (data program-
ming and verification) will start.
Whether the write operation is completed can be confirmed by
_____
reading the status register or the RY/BY Status Flag of the flash
memory control register. When the program starts, the read status
Table 26 List of software commands (CPU rewrite mode)
register mode is entered automatically and the contents of the sta-
tus register is read at the data bus (DB0 to DB7). The status
register bit 7 (SR7) is set to “0” at the same time the write opera-
tion starts and is returned to “1” upon completion of the write
operation. In this case, the read status register mode remains ac-
tive until the next command is written.
____
The RY/BY Status Flag is “0” (busy) during write operation and “1”
(ready) when the write operation is completed as is the status reg-
ister bit 7.
At program end, program results can be checked by reading bit 4
(SR4) of the status register.
Fig. 91 Program flowchart
Command
Program
Clear status register
Read array
Read status register
X
First bus cycle
Second bus cycle
FF16
7016
5016
4016
Write
XSRD
Read
Write
Erase all blocks2016
Write
X
2016
Write
(Note 1)
WA (Note 2)
WD (Note 2)
Block erase
2016
Write
D016
WriteBA (Note 3)
Mode
Address
Mode
Address
Data
(DB0 to DB7)
(Note 4)
Notes 1: SRD = Status Register Data
2: WA = Write Address, WD = Write Data
3: BA = Block Address to be erased (Input the maximum address of each block.)
4: X denotes a given address in the User ROM area .
Cycle number
1
2
1
2
X
Data
Start
Write 4016
Status register
read
Program
completed
NO
YES
Write address
Write data
SR4 = 0 ?
Program
error
NO
YES
SR7 = 1 ?
or
RY/BY = 1 ?
Write
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