參數(shù)資料
型號： M37641F8FP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80
文件頁數(shù)： 100/140頁
文件大小： 1694K
代理商： M37641F8FP
7641 Group
Rev.4.00
Aug 28, 2006
page 60 of 135
REJ03B0191-0400
Fig. 55 Structure of master CPU bus interface related registers
Data bus buffer status register 0 (address 004916)
DBBS0
Output buffer full flag (OBF0)
0: Buffer empty
1: Buffer full
Input buffer full flag (IBF0)
0: Buffer empty
1: Buffer full
User definable flag (U2)
This flag can be defined by user freely.
A0 flag (A00)
This flag indicates the condition of A0 status when
the IBF0 flag is set.
User definable flag (U4–U7)
This flag can be defined by user freely.
b0
b7
Data bus buffer control register 0 (address 004A16)
DBBC0
OBF0 output enable bit
0: P52 functions as I/O port.
1: P52 functions as OBF0 output pin.
IBF0 output enable bit
0: P53 functions as I/O port.
1: P53 functions as IBF0 output pin.
IBF0 interrupt select bit
0: Occurrence due to data write (A0 = “0”) or
command write (A0 = “1”)
1: Occurrence due to command write (A0 = “1”)
Output buffer 0 empty interrupt disable bit
0: Enabled
1: Disabled
Input buffer 0 full interrupt disable bit
0: Enabled
1: Disabled
Reserved bit (“0” at read/write)
Master CPU bus interface enable bit
0: P54 to P57, P60 to P67 function as I/O ports.
1: P54 to P57, P60 to P67 function as master CPU
bus interface function pins.
Bus interface type select bit
0: RD, WR separate type bus
1: R/W type bus
b0
b7
Data bus buffer status register 1 (address 004D16)
DBBS1
Output buffer full flag (OBF1)
0: Buffer empty
1: Buffer full
Input buffer full flag (IBF1)
0: Buffer empty
1: Buffer full
User definable flag (U2)
This flag can be defined by user freely.
A0 flag (A01)
This flag indicates the condition of A0 status when
the IBF1 flag is set.
User definable flag (U4–U7)
This flag can be defined by user freely.
b0
b7
OBF1 output enable bit
0: P74 functions as I/O port.
1: P74 functions as OBF1 output pin.
IBF1 output enable bit
0: P73 functions as port I/O pin.
1: P73 functions as IBF1 output pin.
IBF1 interrupt select bit
0: Occurrence due to data write (A0 = “0”) or
command write (A0 = “1”)
1: Occurrence due to command write (A0 = “1”)
Output buffer 1 empty interrupt disable bit
0: Enabled
1: Disabled
Input buffer 1 full interrupt disable bit
0: Enabled
1: Disabled
Reserved bit (“0” at read/write)
Data bus buffer function select bit
0 : Single data bus buffer mode
(P72 functions as I/O port.)
1 : Double data bus buffer mode
(P72 functions as S1 input pin.)
b0
b7
Data bus buffer control register 1 (address 004E16)
DBBC1
0
00
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