參數(shù)資料
型號(hào)： M37641F8FP
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80
文件頁(yè)數(shù)： 77/140頁(yè)
文件大?。?/td> 1694K
代理商： M37641F8FP
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7641 Group
Rev.4.00
Aug 28, 2006
page 39 of 135
REJ03B0191-0400
DMAC index and status register (address 003F16)
DMAIS
DMAC channel 0 count register underflow flag (D0UF)
0: No underflow
1: Underflow generated
DMAC channel 0 suspend flag (D0SFI)
0: Not suspended
1: Suspended
DMAC channel 1 count register underflow flag (D1UF)
0: No underflow
1: Underflow generated
DMAC channel 1 suspend flag (D1SFI)
0: Not suspended
1: Suspended
DMAC transfer suspend control bit (DTSC)
0: Suspending only burst transfers during interrupt
process
1: Suspending both burst and cycle steal transfers
during interrupt process
DMAC register reload disable bit (DRLDD)
0: Enabling reload of source and destination registers
of both channels
1: Disabling reload of source and destination registers
of both channels
Reserved bit (“0” at read/write)
Channel index bit (DCI)
0: Channel 0 accessible
1: Channel 1 accessible
DMAC channel x mode register 1 (address 004016)
DMAxM1
DMAC channel x source register increment/decrement
selection bit (DxSRID)
0: Increment after transfer
1: Decrement after transfer
DMAC channel x source register increment/decrement enable
bit (DxSRCE)
0: Increment/Decrement disabled (No change after transfer)
1: Increment/Decrement enabled
DMAC channel x destination register increment/decrement
selection bit (DxDRID)
0: Increment after transfer
1: Decrement after transfer
DMAC channel x destination register increment/decrement
enable bit (DxDRCE)
0: Increment/Decrement disabled (No change after transfer)
1: Increment/Decrement enabled
DMAC channel x data write control bit (DxDWC)
0: Writing data in reload latches and registers
1: Writing data in reload latches only
DMAC channel x disable after count register underflow
enable bit (DxDAUE)
0: Channel x enabled after count register underflow
1: Channel x disabled after count register underflow
DMAC channel x register reload bit (DxRLD)
0: Not reloaded (Bit is always read as “0”)
1: Source, destination, and transfer count registers contents
of channel x to be reloaded
DMAC channel x transfer mode selection bit (DxTMS)
0: Cycle steal transfer mode
1: Burst transfer mode
DMAC channel 0 hardware transfer request source bits
(D0HR)
b3b2b1b0
0 0 0 0: Not used
0 0 0 1: UART1 receive interrupt
0 0 1 0: UART1 transmit interrupt
0 0 1 1: Timer Y interrupt
0 1 0 0: INT0 interrupt
0 1 0 1: USB endpoint 1 IN_PKT_RDY signal
(falling edge active)
0 1 1 0: USB endpoint 2 IN_PKT_RDY signal
(falling edge active)
0 1 1 1: USB endpoint 3 IN_PKT_RDY signal
(falling edge active)
1 0 0 0: USB endpoint 1 OUT_PKT_RDY signal
(rising edge active)
1 0 0 1: USB endpoint 1 OUT_FIFO_NOT_EMPTY signal
(rising edge active)
1 0 1 0: USB endpoint 2 OUT_PKT_RDY signal
(rising edge active)
1 0 1 1: USB endpoint 3 OUT_PKT_RDY signal
(rising edge active)
1 1 0 0: Master CPU bus interface OBE0 signal
(rising edge active)
1 1 0 1: Master CPU bus interface IBF0 signal, data
(rising edge active)
1 1 1 0: Serial I/O trasmit/receive interrupt
1 1 1 1: CNTR1 interrupt
DMAC channel 0 software transfer trigger (D0SWT)
0: No action (Bit is always read as “0”)
1: Request of channel 0 transfer by writing “1” (Note 1)
DMAC channel 0 USB and master CPU bus interface enable
bit (D0UMIE)
0: Disabled
1: Enabled
DMAC channel 0 transfer initiation source capture register
reset bit (D0CRR)
0: No action (Bit is always read as “0”)
1: Reset of channel 0 capture register by writing “1” (Note 1)
DMAC channel 0 enable bit (D0CEN)
0: Channel 0 disabled
1: Channel 0 enabled (Note 2)
DMAC channel 0 mode register 2 (address 004116)
DMA0M2
DMAC channel 1 hardware transfer request source bits
(D1HR)
b3b2b1b0
0 0 0 0: Not used
0 0 0 1: UART2 receive interrupt
0 0 1 0: UART2 transmit interrupt
0 0 1 1: Timer X interrupt
0 1 0 0: INT1 interrupt
0 1 0 1: USB endpoint 1 IN_PKT_RDY signal
(falling edge active)
0 1 1 0: USB endpoint 2 IN_PKT_RDY signal
(falling edge active)
0 1 1 1: USB endpoint 4 IN_PKT_RDY signal
(falling edge active)
1 0 0 0: USB endpoint 1 OUT_PKT_RDY signal
(rising edge active)
1 0 0 1: USB endpoint 1 OUT_FIFO_NOT_EMPTY signal
(rising edge active)
1 0 1 0: USB endpoint 2 OUT_PKT_RDY signal
(rising edge active)
1 0 1 1: USB endpoint 4 OUT_PKT_RDY signal
(rising edge active)
1 1 0 0: Master CPU bus interface OBE1 signal
(rising edge active)
1 1 0 1: Master CPU bus interface IBF1 signal, data
(rising edge active)
1 1 1 0: Timer 1 trasmit/receive interrupt
1 1 1 1: CNTR0 interrupt
DMAC channel 1 software transfer trigger (D1SWT)
0: No action (Bit is always read as “0”)
1: Request of channel 0 transfer by writing “1” (Note 1)
DMAC channel 1 USB and master CPU bus interface enable
bit (D1UMIE)
0: Disabled
1: Enabled
DMAC channel 1 transfer initiation source capture register
reset bit (D1CRR)
0: No action (Bit is always read as “0”)
1: Reset of channel 1 capture register by writing “1” (Note 1)
DMAC channel 1 enable bit (D1CEN)
0: Channel 0 disabled
1: Channel 0 enabled (Note 2)
DMAC channel 1 mode register 2 (address 004116)
DMA1M2
b0
b7
b0
b7
b0
b7
b0
b7
Notes 1: This bit is automatically cleared to “0” after writing “1”.
2: When setting this bit to “1”, simultaneously set the DMAC channel x transfer initiation source capture register reset bit (bit 6 of DMAxM2) to “1”.
Fig. 32 Structure of DMACx related register
相關(guān)PDF資料
PDF描述
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