參數(shù)資料
型號(hào)： M37641F8FP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM, PLASTIC, QFP-80
文件頁數(shù)： 68/140頁
文件大?。?/td> 1694K
代理商： M37641F8FP
7641 Group
Rev.4.00
Aug 28, 2006
page 31 of 135
REJ03B0191-0400
qSPI Compatible Mode Operation
Setting the SPI Mode Select Bit (bit 0 of SIOCON2) puts the serial
I/O in SPI compatible mode. The Synchronous Clock Select Bit
(bit 6 of SIOCON1) determines whether the serial I/O is an SPI
master or slave. When the external clock is selected (“0”), the se-
rial I/O is in slave mode; When the internal clock is selected (“1”),
the serial I/O is in master mode.
In SPI compatible mode the SRXD pin functions as a MISO (Mas-
ter In/Slave Out) pin and the STXD pin functions as a MOSI
(Master Out/Slave In) pin.
In slave mode the transmit data is output from the MISO pin and
the receive data is input from the MISO pin. The SRDY pin func-
tions as the chip-select signal input pin from an external.
In master mode the transmit data is output from the MOSI pin and
the receive data is input from the MISO pin. The SRDY pin func-
tions as the chip-select signal output pin to an external.
Slave Mode Operation
In slave mode of SPI compatible mode 4 types of clock polarity
and clock phase can be usable by bits 3 and 4 of serial I/O control
register 2.
If the SRDY pin is held “H”, the shift clock is inhibited, the serial I/
O counter is set to “7”. If the SRDY pin is held “L”, then the shift
clock will start.
Make sure during transfer to maintain the SRDY input at “L” and
not to write data to the serial I/O counter.
Figure 25 shows the serial I/O timing.
相關(guān)PDF資料
PDF描述
M37641M8-XXXFP 8-BIT, MROM, 24 MHz, MICROCONTROLLER, PQFP80
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M37643F8HP 8-BIT, FLASH, 12 MHz, MICROCONTROLLER, PQFP80
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參數(shù)描述
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