參數(shù)資料
型號(hào)： M37274MA
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 8 Bits Microcomputer(8位單片機(jī))
中文描述： 單芯片8位單片機(jī)（8位單片機(jī)）
文件頁數(shù)： 58/131頁
文件大?。?/td> 2049K
代理商： M37274MA
58
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
M37274MA-XXXSP
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
MITSUBISHI MICROCOMPUTERS
The display position in the vertical direction is determined by count-
ing the horizontal sync signal (H
SYNC
). At this time, when V
SYNC
and
H
SYNC
are positive polarity (negative polarity), it starts to count the
rising edge (falling edge) of H
SYNC
signal from after fixed cycle of
rising edge (falling edge) of V
SYNC
signal. So interval from rising edge
(falling edge) of V
SYNC
signal to rising edge (falling edge) of H
SYNC
signal needs enough time (2 machine cycles or more) for avoiding
jitter. The polarity of H
SYNC
and V
SYNC
signals can select with the
I/O polarity control register (address 0217
16
).
Fig. 60. Supplement Explanation for Display Position
The vertical position for each block can be set in 1024 steps (where
each step is 1T
H
(T
H
: H
SYNC
cycle)) as values “00
16
” to “FF
16
” in
vertical position register 1i (i = 1 to 12) (addresses 0220
16
to 022B
16
)
and values “00
16
” to “03
16
” in vertical position register 2i (i = 1 to 12)
(addresses 0230
16
to 023B
16
). The structure of the vertical position
registers is shown in Figure 61.
Fig. 61. Vertical Position Registers
The horizontal position is common to all blocks, and can be set in
256 steps (where 1 step is 4T
OSC
, T
OSC
being the oscillating cycle
for display) as values “00
16
” to “FF
16
” in bits 0 to 7 of the horizontal
position register (address 00CF
16
). The structure of the horizontal
position register is shown in Figure 62.
Fig. 62. Horizontal Position Register
When bits 0 and 1 of the I/O polarity control register
(address 0217
16
) are set to “1” (negative polarity)
V
SYNC
signal input
SYNC
control
V
Period signal
H
0.25 to 0.50 [
μ
s]
( at f(X
IN
) = 8MHz)
(Note 2)
SYNC
H
Not count
1
2
3
4
5
Notes 1 :
The vertical position is determined by counting falling edge of
H
SYNC
signal after rising edge of V
SYNC
control signal in the
microcomputer.
2 :
Do not generate falling edge of H
SYNC
signal near rising edge
of V
SYNC
control signal in microcomputer to avoid jitter.
3 :
The pulse width of V
SYNC
and H
SYNC
needs 8 machine cycles
or more.
8 machine cycles
8 machine cycles
7
Vertical position register 1i
(i = 1 to 12)
(VP1i : addresses 0220
16
to 022B
16
)
Control bits of vertical display
start positions (Note)
Vertical display start positions (low-order 8 bits)
T
H
(setting value of low-order 2 bits of VP2i
16
+
setting value of low-order 4 bits of VP1i
16
+
setting value of low-order 4 bits of VP1i
16 )
Note :
Set values except “00
16
” and “01
16
” to VP1i when VP2i is “00
16.
”
2
1
0
7
Vertical position register 2i
(i = 1 to 12)
(VP2i : addresses 0230
16
to 023B
16
)
Control bits of vertical display
start positions (Note)
Vertical display start positions (high-order 2 bits)
T
H
(setting value of low-order 2 bits of VP2i
16
setting value of low-order 4 bits of VP1i
16
setting value of low-order 4 bits of VP1i
16 )
+
2
1
0
Note
:
The setting value synchronizes with the V
SYNC
.
7
Horizontal position register
(HP : address 00CF
16
)
Control bits of horizontal display
start positions
Horizontal display start positions
4T
OSC
(setting value of high-order 4 bits
16
+
setting value of low-order 4 bits
16 )
1
0
+
0
0
0
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