參數(shù)資料
型號(hào)： M37274MA
廠商： Mitsubishi Electric Corporation
英文描述： Single Chip 8 Bits Microcomputer(8位單片機(jī))
中文描述： 單芯片8位單片機(jī)（8位單片機(jī)）
文件頁數(shù)： 44/131頁
文件大小： 2049K
代理商： M37274MA
44
MITSUBISHI MICROCOMPUTERS
M37274MA-XXXSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
PRELIMINARY
Notice: This is not a final specification.
Some paramentic limits are subject to change.
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
Slave address
I
2
C address register
(S0D: address 00F7
16
)
Read/write bit
7
0
(1) I
2
C Data Shift Register
The I
2
C data shift register (S0 : address 00F6
16
) is an 8-bit shift
register to store receive data and write transmit data.
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
The I
2
C data shift register is in a write enable status only when the
ESO bit of the I
2
C control register (address 00F9
16
) is “1.” The bit
counter is reset by a write instruction to the I
2
C data shift register.
When both the ESO bit and the MST bit of the I
2
C status register
(address 00F8
16
) are “1,” the SCL is output by a write instruction to
the I
2
C data shift register. Reading data from the I
2
C data shift regis-
ter is always enabled regardless of the ESO bit value.
Note:
To write data into the I
2
C data shift register after setting the
MST bit to “0” (slave mode), keep an interval of 8 machine
cycles or more.
(2) I
2
C Address Register
The I
2
C address register (address 00F7
16
) consists of a 7-bit slave
address and a
read
/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition are detected.
I
Bit 0:
Read
/Write Bit (RBW)
Not used when comparing addresses, in the 7-bit addressing mode.
In the 10-bit addressing mode, the first address data to be received
is compared with the contents (SAD6 to SAD0 + RBW) of the I
2
C
address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
I
Bits 1 to 7: Slave Address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data trans-
mitted from the master is compared with the contents of these bits.
(3) I
2
C Clock Control Register
The I
2
C clock control register (address 00FA
16
) is used to set ACK
control, SCL mode and SCL frequency.
I
Bits 0 to 4: SCL Frequency Control Bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 7.
I
Bit 5: SCL Mode Specification Bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the stan-
dard clock mode is set. When the bit is set to “1,” the high-speed
clock mode is set.
I
Bit 6: ACK Bit (ACK BIT)
This bit sets the SDA status when an ACK clock
8
is generated. When
this bit is set to “0,” the ACK return mode is set and SDA goes to
LOW at the occurrence of an ACK clock. When the bit is set to “1,”
the ACK non-return mode is set. The SDA is held in the HIGH status
at the occurrence of an ACK clock.
However, when the slave address matches the address data in the
reception of address data at ACK BIT = “0,” the SDA is automatically
made LOW (ACK is returned). If there is a mismatch between the
slave address and the address data, the SDA is automatically made
HIGH (ACK is not returned).
8
ACK clock: Clock for acknowledgement
I
Bit 7: ACK Clock Bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowl-
edgment response of data transmission. When this bit is set to “0,”
the no ACK clock mode is set. In this case, no ACK clock occurs
after data transmission. When the bit is set to “1,” the ACK clock
mode is set and the master generates an ACK clock upon comple-
tion of each 1-byte data transmission.The device for transmitting
address data and control data releases the SDA at the occurrence of
an ACK clock (make SDA HIGH) and receives the ACK bit gener-
ated by the data receiving device.
Note:
Do not write data into the I
2
C clock control register during
transmission. If data is written during transmission, the I
2
C
clock generator is reset, so that data cannot be transmitted
normally.
Fig. 43. I
2
C Address Register
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