參數(shù)資料
型號(hào): M34584EDFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO42
封裝: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁數(shù): 8/157頁
文件大?。?/td> 1130K
代理商: M34584EDFP
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Skip condition
Number of
cycles
Number of
words
Instruction
code
D9
D0
Flag CY
2
16
Rev.3.00
2004.08.06
page 105 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
SZD (Skip if Zero, port D specified by register Y)
0000100100
024
22
(D(Y)) = 0
(Y) = 0 to 6
Grouping:
Input/Output operation
Description: Skips the next instruction when a bit of port
D specified by register Y is “0.” Executes the
next instruction when the bit is “1.”
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
1000110000
230
11
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 1 and timer 1 re-
load register R1. Transfers the contents of
register A to the low-order 4 bits of timer 1
and timer 1 reload register R1.
Operation:
(T17–T14)
← (B)
(R17–R14)
← (B)
(T13–T10)
← (A)
(R13–R10)
← (A)
Operation:
(D(Y)) = 0 ?
(Y) = 0 to 6
2
16
0000101011
02B
T2AB (Transfer data to timer 2 and register R2 from Accumulator and register B)
1000110001
231
11
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 2 and timer 2 re-
load register R2. Transfers the contents of
register A to the low-order 4 bits of timer 2
and timer 2 reload register R2.
Operation:
(T27–T24)
← (B)
(R27–R24)
← (B)
(T23–T20)
← (A)
(R23–R20)
← (A)
T3AB (Transfer data to timer 3 and register R3 from Accumulator and register B)
1000110010
232
11
Grouping:
Timer operation
Description: Transfers the contents of register B to the
high-order 4 bits of timer 3 and timer 3 re-
load register R3. Transfers the contents of
register A to the low-order 4 bits of timer 3
and timer 3 reload register R3.
Operation:
(T37–T34)
← (B)
(R37–R34)
← (B)
(T33–T30)
← (A)
(R33–R30)
← (A)
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