參數(shù)資料
型號： M34584EDFP
元件分類： 微控制器/微處理器
英文描述： 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO42
封裝： 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁數(shù)： 131/157頁
文件大?。?/td> 1130K
代理商： M34584EDFP
Rev.3.00
2004.08.06
page 75 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Falling edge
Rising edge
Falling edge
Rising edge
CNTR1 output auto-control circuit not selected
CNTR1 output auto-control circuit selected
D6 (I/O) / CNTR0 (input)
CNTR0 (I/O) /D6 (input)
CNTR1 pin input count edge selection bit
CNTR0 pin input count edge selection bit
CNTR1 output auto-control circuit
selection bit
D6/CNTR0 pin function selection bit
0
1
0
1
0
1
0
1
Timer control register W6
at RAM back-up : state retained
at reset : 00002
W63
W62
W61
W60
CNTR1 output invalid
CNTR1 output valid
PWM signal “H” interval expansion function invalid
PWM signal “H” interval expansion function valid
Stop (state retained)
Operating
XIN input
Prescaler output (ORCLK) divided by 2
CNTR1 pin function selection bit
PWM signal
“H” interval expansion function control bit
Timer 4 control bit
Timer 4 count source selection bit
0
1
0
1
0
1
0
1
W43
W42
W41
W40
W51
0
1
Not used
Period measurement circuit control bit
Signal for period measurement selection
bits
0
1
0
1
W50
0
1
0
1
Timer control register W5
at RAM back-up : state retained
at reset : 00002
W53
W52
W51
W50
This bit has no function, but read/write is enabled.
Stop
Operating
Count source
On-chip oscillator (f(RING/16))
CNTR0 pin input
INT0 pin input
Not available
R/W
TAW4/TW4A
Timer control register W4
at RAM back-up : 00002
at reset : 00002
R/W
TAW5/TW5A
R/W
TAW6/TW6A
W31
0
1
Timer 3 count auto-stop circuit not selected
Timer 3 count auto-stop circuit selected
Stop (state retained)
Operating
Count source
PWM signal (PWMOUT)
Prescaler output (ORCLK)
Timer 2 underflow signal (T2UDF)
CNTR1 input
Timer 3 count auto-stop circuit selection
bit (Note 2)
Timer 3 control bit
Timer 3 count source selection bits
(Note 3)
0
1
0
1
W30
0
1
0
1
Timer control register W3
at RAM back-up : state retained
at reset : 00002
W33
W32
W31
W30
R/W
TAW3/TW3A
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: This function is valid only when the timer 3 count start synchronous circuit is selected (I20=“1”).
3: The port C output is invalid when CNTR1 output is selected for the timer 3 count source.
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參數(shù)描述
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