參數資料
型號: M34584EDFP
元件分類: 微控制器/微處理器
英文描述: 4-BIT, OTPROM, 6 MHz, MICROCONTROLLER, PDSO42
封裝: 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁數: 58/157頁
文件大?。?/td> 1130K
代理商: M34584EDFP
Rev.3.00
2004.08.06
page 150 of 155
REJ03B0010-0300Z
4584 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A/D CONVERTER RECOMMENDED OPERATING CONDITIONS
(Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted)
Symbol
VDD
VIA
f(ADCK)
Parameter
Supply voltage
Analog input voltage
A/D conversion clock
frequency
(Note)
Conditions
Unit
V
kHz
Mask ROM version
One Time PROM version
Mask ROM version
One Time PROM version
Min.
2.0
3.0
0
0.8
Typ.
Max.
5.5
VDD
334
245
3.9
1.8
334
123
Limits
VDD = 4.0 to 5.5 V
VDD = 2.7 to 5.5 V
VDD = 2.2 to 5.5 V
VDD = 2.0 to 5.5 V
VDD = 4.0 to 5.5 V
VDD = 3.0 to 5.5 V
Note: Definition of A/D conversion clock (ADCK)
<Operating condition map of A/D conversion clock (ADCK) >
334
245
(123)
2.2
( ): One Time PROM version
2.7
(3.0)
4
2
5.5
VDD[V]
3.9
(15.3)
1.8
0.8
f(ADCK)
[kHz]
Recommended
operating operation
11
10
01
00
0
1
Instruction clock (INSTCK)
On-chip oscillator clock(RING)
A/D conversion clock (ADCK)
Division circuit
System clock (STCK)
Instruction clock
(INSTCK)
Multi-
plexer
(CMCK,
CRCK,
CYCK)
MR0
1
0
MR3, MR2
01
00
10
11
On-chip oscillator
XIN
Ceramic resonance
RC oscillation
Internal clock
generating circuit
(divided by 3)
Quartz-crystal
oscillation
On-chip oscillator clock (RING)
Q31, Q30
Q32
Divided by 2
Divided by 4
Divided by 8
Division circuit
Divided by 12
Divided by 24
Divided by 48
Divided by 6
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