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參數(shù)資料
| 型號(hào)： | M32180F8VFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP240 |
| 封裝： | 32 X 32 MM, 0.50 MM PITCH, PLASTIC, QFP-240 |
| 文件頁數(shù)： | 87/139頁 |
| 文件大?。?/td> | 3774K |
| 代理商： | M32180F8VFP |
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2
2-14
32180 Group User’s Manual (Rev.1.0)
CPU
2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK
Instruction Execution
The LOCK bit is set when executing the BSET or BCLR instruction, and is cleared when the BSET or BCLR
instruction finishes.
The LOCK instruction sets the LOCK bit, as well as performs an ordinary load operation. The UNLOCK instruction
is used to clear the LOCK bit.
The LOCK bit is located inside the CPU, and cannot directly be accessed for read or write by users. This bit
controls granting of bus control requested by devices other than the CPU.
When LOCK bit = "0"
Control of the bus requested by devices other than the CPU is granted
When LOCK bit = "1"
Control of the bus requested by devices other than the CPU is denied
In the 32180 group, control of the bus may be requested by devices other than the CPU in the following two cases:
When DMA transfer is requested by the internal DMAC
When HREQ# input is pulled low to request that the CPU be placed in a hold state
2.8 Precautions on CPU
Usage Notes for 0 Division Instruction
Problem and Conditions
Inaccurate calculations for the instructions listed in (2) will result from execution of the 0 division instruction
under the conditions described in (1).
(1) If 0 division calculation is executed when the divisor = 0 for instructions DIV, DIVU, REM and REMU,
(2) the result will be inaccurate calculations for any of the following instructions that are executed immedi-
ately after 0 division:
ADDV, ADDX, ADD, ADDI, ADDV3, ADD3,
CMP, CMPU, CMPI, CMPUI,
SUBV, SUBX, SUB,
DIV, DIVU,
REM, REMU.
Countermeasure
Assuming that the 0 division occurrence itself is not expected by the system and therefore is the cause of
miscalculations, before executing division or remainder instructions, do a 0 check on the divisor to make sure 0
division does not occur.
2.7 Supplementary Explanation for BSET, BCLR, LOCK and UNLOCK Instruction Execution
相關(guān)PDF資料 |
PDF描述 |
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| M32182F3VFP | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144 |
| M32182F3UFP | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144 |
| M32182F3TFP | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144 |
| M32182F3VFP | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144 |
| M32182F3TFP | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M32180T2-PTC | 功能描述:DEV CONNECTION CNVTR FOR 32180 G RoHS:否 類別:編程器，開發(fā)系統(tǒng) >> 配件 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標(biāo)準(zhǔn)包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關(guān)產(chǎn)品:1-Wire? 設(shè)備 產(chǎn)品目錄頁面:1429 (CN2011-ZH PDF) |
| M32182F3TFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F3UFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F3VFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
| M32182F8TFP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES |
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