參數(shù)資料
型號(hào): M32180F8VFP
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP240
封裝: 32 X 32 MM, 0.50 MM PITCH, PLASTIC, QFP-240
文件頁(yè)數(shù): 77/139頁(yè)
文件大?。?/td> 3774K
代理商: M32180F8VFP
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)當(dāng)前第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)
2
2-5
32180 Group User’s Manual (Rev.1.0)
CPU
2.3.5 Floating-point Status Register: FPSR (CR7)
0000
0
0000000
2
3
4
5
6
7
8
9
10
11
12
13
14
b15
1
b0
0
00000100000000
EV
DN
CE
CX
CU
CZ
CO
CV
RM
18
19
20
21
22
23
24
25
26
27
28
29
30
b31
17
b16
EU
EX
FS
FX
FU
FZ
0
FO
0
FV
EZ
EO
<After reset: H’0000 0100>
b
Bit Name
Function
R
W
0
FS
Reflects the logical sum of FU, FZ, FO and FV.
R
Floating-point Exception Summary Bit
1
FX
Set to "1" when an inexact exception occurs (if EIT processing is
R
W
Inexact Exception Flag
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
2
FU
Set to "1" when an underflow exception occurs (if EIT processing is
R
W
Underflow Exception Flag
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
3
FZ
Set to "1" when a zero divide exception occurs (if EIT processing is
R
W
Zero Divide Exception Flag
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
4
FO
Set to "1" when an overflow exception occurs (if EIT processing is
R
W
Overflow Exception Flag
unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
5
FV
Set to "1" when an invalid operation exception occurs (if EIT processing
R
W
Invalid Operation Exception Flag
is unexecuted (Note 1)). Once set, the flag retains the value "1" until
it is cleared to "0" in software.
6–16
No function assigned. Fix to "0".
00
17
EX
0: Mask EIT processing to be executed when an inexact exception occurs.
R
W
Inexact Exception Enable Bit
1: Execute EIT processing when an inexact exception occurs.
18
EU
0: Mask EIT processing to be executed when an underflow exception
R
W
Underflow Exception Enable Bit
occurs.
1: Execute EIT processing when an underflow exception occurs.
19
EZ
0: Mask EIT processing to be executed when a zero divide exception
R
W
Zero Divide Exception Enable Bit
occurs.
1: Execute EIT processing when a zero divide exception occurs.
20
EO
0: Mask EIT processing to be executed when an overflow exception
R
W
Overflow Exception Enable Bit
occurs.
1: Execute EIT processing when an overflow exception occurs.
21
EV
0: Mask EIT processing to be executed when an invalid operation
R
W
Invalid Operation Exception Enable Bit
exception occurs.
1: Execute EIT processing when an invalid operation exception occurs.
22
No function assigned. Fix to "0".
00
23
DN
0: Handle the denormalized number as a denormalized number.
R
W
Denormalized Number Zero Flush Bit
1: Handle the denormalized number as zero.
(Note 2)
24
CE
0: No unimplemented operation exception occurred.
R (Note 3)
Unimplemented Operation
1: An unimplemented operation exception occurred. When the bit is
Exception Cause Bit
set to "1", the execution of an FPU operation instruction will clear it to "0".
25
CX
0: No inexact exception occurred.
R (Note 3)
Inexact Exception Cause Bit
1: An inexact exception occurred. When the bit is set to "1",
the execution of an FPU operation instruction will clear it to "0".
2.3 Control Registers
相關(guān)PDF資料
PDF描述
M32182F3VFP 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144
M32182F3UFP 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
M32182F3TFP 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
M32182F3VFP 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP144
M32182F3TFP 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQFP144
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M32180T2-PTC 功能描述:DEV CONNECTION CNVTR FOR 32180 G RoHS:否 類別:編程器,開發(fā)系統(tǒng) >> 配件 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program RoHS指令信息:IButton RoHS Compliance Plan 標(biāo)準(zhǔn)包裝:1 系列:- 附件類型:USB 至 1-Wire? RJ11 適配器 適用于相關(guān)產(chǎn)品:1-Wire? 設(shè)備 產(chǎn)品目錄頁(yè)面:1429 (CN2011-ZH PDF)
M32182F3TFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
M32182F3UFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
M32182F3VFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES
M32182F8TFP 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:32-BIT RISC SINGLE-CHIP MICROCOMPUTER M32R FAMILY / M32R/ECU SERIES