參數(shù)資料
型號： M32180F8VFP
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP240
封裝： 32 X 32 MM, 0.50 MM PITCH, PLASTIC, QFP-240
文件頁數(shù)： 30/139頁
文件大?。?/td> 3774K
代理商： M32180F8VFP
5
5-14
INTERRUPT CONTROLLER (ICU)
32180 Group User’s Manual (Rev.1.0)
5.5 Description of Interrupt Operation
Table 5.5.1 Hardware Fixed Priority Levels
Priority
Interrupt Request Source
ICU Vector Table Address
ICU Type of Input Source
High
TIN3–6 input interrupt request
H'0000 0094
–
H'0000 0097
Level-recognized
TIN20–29 input interrupt request
H'0000 0098
–
H'0000 009B
Level-recognized
TIN12–19 input interrupt request
H'0000 009C
–
H'0000 009F
Level-recognized
TIN0–2 input interrupt request
H'0000 00A0
–
H'0000 00A3
Level-recognized
TIN7–11 input interrupt request
H'0000 00A4
–
H'0000 00A7
Level-recognized
TMS0,1 output interrupt request
H'0000 00A8
–
H'0000 00AB
Level-recognized
TOP8,9 output interrupt request
H'0000 00AC
–
H'0000 00AF
Level-recognized
TOP10 output interrupt request
H'0000 00B0
–
H'0000 00B3
Edge-recognized
TIO4–7 output interrupt request
H'0000 00B4
–
H'0000 00B7
Level-recognized
TIO8,9 output interrupt request
H'0000 00B8
–
H'0000 00BB
Level-recognized
TOP0–5 output interrupt request
H'0000 00BC
–
H'0000 00BF
Level-recognized
TOP6,7 output interrupt request
H'0000 00C0
–
H'0000 00C3
Level-recognized
TIO0–3 output interrupt request
H'0000 00C4
–
H'0000 00C7
Level-recognized
DMA0–4 interrupt request
H'0000 00C8
–
H'0000 00CB
Level-recognized
SIO1 receive interrupt request
H'0000 00CC
–
H'0000 00CF
Edge-recognized
SIO1 transmit interrupt request
H'0000 00D0
–
H'0000 00D3
Edge-recognized
SIO0 receive interrupt request
H'0000 00D4
–
H'0000 00D7
Edge-recognized
SIO0 transmit interrupt request
H'0000 00D8
–
H'0000 00D8
Edge-recognized
A-D0 conversion interrupt request
H'0000 00DC
–
H'0000 00DF
Edge-recognized
TID0 output interrupt request
H'0000 00E0
–
H'0000 00E3
Edge-recognized
TOU0 output interrupt request
H'0000 00E4
–
H'0000 00E7
Level-recognized
DMA5–9 interrupt request
H'0000 00E8
–
H'0000 00EB
Level-recognized
SIO2,3 transmit/receive interrupt request H'0000 00EC
–
H'0000 00EF
Level-recognized
RTD interrupt request
H'0000 00F0
–
H'0000 00F3
Edge-recognized
TID1 output interrupt request
H'0000 00F4
–
H'0000 00F7
Edge-recognized
TOU1,2 output interrupt request
H'0000 00F8
–
H'0000 00FB
Level-recognized
SIO4,5 transmit/receive interrupt request H'0000 00FC
–
H'0000 00FF
Level-recognized
A-D1 conversion interrupt request
H'0000 0100
–
H'0000 0103
Edge-recognized
TID2 output interrupt request
H'0000 0104
–
H'0000 0107
Edge-recognized
TIN30–33 input interrupt request
H'0000 0108
–
H'0000 010B
Level-recognized
CAN0 transmit/receive & error interrupt
H'0000 010C
–
H'0000 010F
Level-recognized
request
CAN1 transmit/receive & error interrupt
H'0000 0110
–
H'0000 0113
Level-recognized
Low
request
Table 5.5.2 ILEVEL Settings and Accepted IMASK Values
ILEVEL values set
IMASK values at which interrupts are accepted
0 (ILEVEL = "000")
Accepted when IMASK is 1–7
1 (ILEVEL = "001")
Accepted when IMASK is 2–7
2 (ILEVEL = "010")
Accepted when IMASK is 3–7
3 (ILEVEL = "011")
Accepted when IMASK is 4–7
4 (ILEVEL = "100")
Accepted when IMASK is 5–7
5 (ILEVEL = "101")
Accepted when IMASK is 6–7
6 (ILEVEL = "110")
Accepted when IMASK is 7
7 (ILEVEL = "111")
Not accepted (interrupts disabled)
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