7. Clock Generation Circuit
page 54
9
2
3
f
o
7
0
2
,
5
1
.
b
e
F
0
.
2
.
v
e
R
0
2
0
-
2
0
2
0
B
9
0
J
E
R
)
T
6
2
/
C
6
1
M
,
B
6
2
/
C
6
1
M
,
A
6
2
/
C
6
1
M
(
p
u
o
r
G
A
6
2
/
C
6
1
M
Figure 7.6.1. State Transition to Stop Mode and Wait Mode
Figure 7.6.1 shows the state transition from normal operation mode to stop mode and wait mode. Figure
7.6.1.1 shows the state transition in normal operation mode.
Table 7.6.1 shows a state transition matrix describing allowed transition and setting. The vertical line
shows current state and horizontal line shows state after transition.
Reset
Medium-speed mode
(divided-by-8 mode)
High-speed, medium-
speed mode
Stop mode
Wait mode
Interrupt
Low-speed mode
Stop mode
Interrupt
Wait mode
Interrupt
Stop mode
All oscillators stopped
Interrupt
Wait mode
WAIT
instruction
Interrupt
CPU operation stopped
PLL operation
mode
(1, 2)
Wait mode
Interrupt
CM10=1(6)
Interrupt(4)
Stop mode
WAIT
instruction
WAIT
instruction
WAIT
instruction
On-chip oscillator mode
(selectable frequency)
On-chip oscillator
mode (f2(ROC)/16)
Normal operation mode
CM07=0
CM06=1
CM05=0
CM11=0
CM10=1
(5)
On-chip oscillator low power
dissipation mode
Stop mode
Interrupt(4)
Wait mode
Interrupt
WAIT
instruction
CM05, CM06, CM07: Bits in the CM0 register
CM10, CM11: Bits in the CM1 register
CM10=1(6)
Low power dissipation mode
Stop mode
Interrupt
Wait mode
Interrupt
WAIT
instruction
CM21=1
CM21=0
CM10=1(6)
(7)
: Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown.
NOTES:
1. Do not go directly from PLL operation mode to wait or stop mode.
2. PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.
3. When the PM21 bit is set to 0 (system clock protective function unused).
4. The on-chip oscillator clock divided by 8 provides the CPU clock.
5. Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21 bit is set to 0 (on-chip oscillator
turned off). When the clock generated externally is input to the XCIN pin, transit to stop mode with this process.
6. Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to 0 (oscillation stop and oscillation restart detection
function disabled).
7. The CM06 bit is set to 1 (divide-by-8).