14. A/D Converter
page 185
9
2
3
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o
7
0
2
,
5
1
.
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F
0
.
2
.
v
e
R
0
2
0
-
2
0
2
0
B
9
0
J
E
R
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T
6
2
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C
6
1
M
,
B
6
2
/
C
6
1
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,
A
6
2
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C
6
1
M
(
p
u
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G
A
6
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6
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Figure 14.5 TB2SC Register
PWCOM
Symbol
Address
After reset
TB2SC
039E16
X00000002
Timer B2 Reload Timing
Switch Bit
0 : Timer B2 underflow
1 : Timer A output at odd-numbered
Timer B2 special mode register (1)
Bit name
Function
Bit symbol
b7
b6
b5
b4
b3
b2
b1
b0
IVPCR1
Three-Phase Output Port
SD Control Bit 1
0 : Three-phase output forcible cutoff
by SD pin input (high impedance)
disabled
1 : Three-phase output forcible cutoff
by SD pin input (high impedance)
enabled
RW
Nothing is assigned. When write, set to “0”.
When read, its content is “0”.
(b7)
TB2SEL
Trigger Select Bit
0 : TB2 interrupt
1 : Underflow of TB2 interrupt
generation frequency setting counter [ICTB2]
RW
TB0EN
Timer B0 Operation Mode
Select Bit
0 : Other than A/D trigger mode
1 : A/D trigger mode (5)
RW
TB1EN
Timer B1 Operation Mode
Select Bit
0 : Other than A/D trigger mode
1 : A/D trigger mode (5)
RW
(2)
(3, 4, 7)
(6)
(b6-b5)
Reserved bits
Must set to "0"
0
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).
2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this bit to
"0" (timer B2 underflow).
3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5 bit to
"0" (= input mode).
4. Related pins are U(P80), U(P81), V(P72), V(P73), W(P74), W(P75). When a high-level ("H") signal is applied to the SD
pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state.
If a low-level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0).
At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1
bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those
pins is used.
5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).
6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the
INV02 bit to "1" (three-phase motor control timer function).
7. Refer to 16.6 Digital Debounce function for SD input.