參數(shù)資料
型號: M2V64S3DTP-6
廠商: Mitsubishi Electric Corporation
英文描述: 64M Synchronous DRAM
中文描述: 6400同步DRAM
文件頁數(shù): 3/51頁
文件大?。?/td> 430K
代理商: M2V64S3DTP-6
Feb.'00
MITSUBISHI LSIs
MITSUBISHI ELECTRIC
SDRAM (Rev.3.2)
64M Synchronous DRAM
M2V64S20DTP-6,-6L,-7,-7L,-8,-8L
M2V64S30DTP-6,-6L,-7,-7L,-8,-8L
M2V64S40DTP-6,-6L,-7,-7L,-8,-8L
(4-BANK x 4,194,304-WORD x 4-BIT)
(4-BANK x 2,097,152-WORD x 8-BIT)
(4-BANK x 1,048,576-WORD x 16-BIT)
3
BLOCK DIAGRAM
Type Designation Code
M2 V 64 S 3 0
TP
-8
Access Item
Package Type
Process Generation D : 5th gen.
Interface
Organization
Synchronous DRAM
Density
Function
Mitsubishi DRAM
These rules are only applied to the Synchronous DRAM family.
Note : This figure shows the M2V64S30DTP.
The M2V64S20DTP configration is 4096x1024x4 of cell array and DQ 0-3.
The M2V64S40DTP configration is 4096x256x16 of cell array and DQ 0-15.
Address Buffer
A0-11
BA0,1
Control Signal Buffer
/CS
/RAS
/CAS
/WE
CLK
CKE
Clock Buffer
Control Circuitry
I/O Buffer
DQ0-7
Mode
Register
DQM
Memory Array
4096 x512 x8
Cell Array
Bank #0
Memory Array
4096 x512 x8
Cell Array
Bank #1
Memory Array
4096 x512 x8
Cell Array
Bank #2
Memory Array
4096 x512 x8
Cell Array
Bank #3
D
-6 : 7.5ns (PC133 3-3-3),
-7 : 10ns (PC100 2-2-2),
-8 : 10ns (PC100 3-2-2)
TP: TSOP(II)
Reserved for Future Use
2 : x4, 3 : x8, 4 : x16
64 : 64Mbit
V : LVTTL
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