參數(shù)資料
型號(hào)： M-ORSO82G52BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁數(shù)： 85/123頁
文件大小： 2207K
代理商： M-ORSO82G52BM680-DB
Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
64
Reset Conditions
The SERDES block can be reset in one of three different ways: on power up, using the hardware reset
(PASB_RESETN) or by setting bits in the control registers. The power up reset process begins when the power
supply voltage ramps up to approximately 80% of the nominal value of 1.5 V. Following this event, the device will be
ready for normal operation after 3 ms.
A hardware reset is initiated by making the PASB_RESETN low for at least two microprocessor clock cycles. The
device will be ready for operation 3 ms after the low to high transition of the PASB_RESETN. This reset function
affects all SERDES blocks and resets all core control, status and data path registers and counters.
Using the software reset option, each channel can be individually reset by setting SWRST bit to a logic 1 in the
SERDES channel conguration register. The device will be ready 3 ms after the SWRST bit is deasserted. Simi-
larly, all four channels per quad SERDES can be reset by setting the global reset bit GSWRST. The device will be
ready for normal operation 3 ms after the GSWRST bit is deasserted. Note that the software reset options resets
only the SERDES internal registers and counters on a per channel or per quad basis. The core non-SERES regis-
ters and logic blocks are not affected. It should also be noted that the embedded core registers and logic blocks
cannot be accessed until after FPGA conguration is complete.
Table 11. summarizes the conditions under which the embedded core registers, SERDES, and embedded core
logic are reset under user control. The embedded core status registers are also reset on read.
Table 11. ORSO82G5 Reset Conditions
Reset Signal
Embedded
Core Non-
SERDES
Registers
SERDES
Registers
and
Blocks
Other
Embedded
Core Blocks
SERDES
I/O
Notes
Powerup
reset
Disabled
Power on reset
PASB_RESETN pin = 0
(Hard Reset)
reset
Disabled
External input pin
FPGA Conguration
reset
Disabled
DONE pin = 0
Partial FPGA Reconguration (with
option disable TRI_IO)
—
Active
DONE pin = 0
Internal Signal FPGA_RESET = 1
—
reset
Active
FPGA_RESET is FPGA
sourced
FPGA GSRN signal = 0
—
reset
Active
GSRN is FPGA sourced. Set
GSRN_DISABLE = 1 to dis-
able this reset
SOFT_RESET = 0, 1, 0
(System Bus register based)
—
reset
Active
write SOFT_RESET = 1 (ON)
then
write SOFT_RESET = 0
(OFF)
TS_ALL Pin = 1
—
Active
External input pin
SWRST_xx= 0,1,0
xx = [AA,...,BD]
—
Selected
channel
reset
—
Active
Per channel software reset
(Not self-clearing, must be
manually set and cleared.)
GSWRST_[A:B] = 0,1,0
—
Selected
quad reset
—
Active
Per quad software reset (Not
self-clearing, must be manu-
ally set and cleared.)
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