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| 型號(hào)： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁(yè)數(shù)： | 69/123頁(yè) |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
5
faster routing times with predictable and efcient performance.
SLIC provides eight 3-statable buffers, up to a 10-bit decoder, and PAL-like AND-OR-Invert (AOI) in each pro-
grammable logic cell.
New 200 MHz embedded quad-port RAM blocks,
2 read ports, 2 write ports, and 2 sets of byte lane enables. Each embedded RAM block can be congured as:
– 1—512 x 18 (quad-port, two read/two write) with optional built in arbitration.
– 1—256 x 36 (dual-port, one read/one write).
– 1—1K x 9 (dual-port, one read/one write).
– 2—512 x 9 (dual-port, one read/one write for each).
–2 RAMS with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write).
– Supports joining of RAM blocks.
–Two 16 x 8-bit Content Addressable Memory (CAM) support.
– FIFO 512 x 18, 256 x 36, 1Kx 9, or dual 512 x 9.
– Constant multiply (8 x 16 or 16 x 8).
– Dual variable multiply (8 x 8).
Embedded 32-bit internal system bus plus 4-bit parity interconnects FPGA logic, MicroProcessor Interface (MPI),
embedded RAM blocks, and embedded standard cell blocks with 100 MHz bus performance. Included are built-
in system registers that act as the control and status center for the device.
Built-in testability:
– Full boundary scan (IEEE 1149.1 and Draft 1149.2 JTAG).
– Programming and readback through boundary scan port compliant to IEEE Draft 1532:D1.7.
– TS_ALL testability function to 3-state all I/O pins.
–New temperature-sensing diode.
Improved built-in clock management with Programmable Phase-Locked Loops (PPLLs) provide optimum clock
modication and conditioning for phase, frequency, and duty cycle from 15 MHz up to 420 MHz. Multiplication of
the input frequency up to 64x and division of the input frequency down to 1/64x possible.
New cycle stealing capability allows a typical 15% to 40% internal speed improvement after nal place and route.
This feature also enables compliance with many setup/hold and clock to out I/O specications and may provide
reduced ground bounce for output buses by allowing exible delays of switching output buffers.
PCI local bus compliant for FPGA I/Os.
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