參數(shù)資料
型號(hào)： M-ORSO82G52BM680-DB
廠商： LATTICE SEMICONDUCTOR CORP
元件分類： FPGA
英文描述： FPGA, 1296 CLBS, 333000 GATES, PBGA680
封裝： PLASTIC, FBGA-680
文件頁數(shù)： 40/123頁
文件大?。?/td> 2207K
代理商： M-ORSO82G52BM680-DB
Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
23
SERDES Transmit Path
The transmitter section accepts 8-bit data at the parallel input port from the MUX block in the internal transmit core.
Data is transmitted with bit 7 sent rst and bit 0 sent last. It also accepts the low-speed reference clock at the REF-
CLK input and uses this clock to synthesize the internal high-speed serial bit clock.
The embedded core uses the XCK311 SERDES output as the reference clock. The frequency of this clock will
depend on the half-rate/full-rate control bit in the SERDES; and the frequency of the REFCLK ports. Transmit tim-
ing is shown in Figure 9.
Figure 9. SERDES Transmit Path Timing
The serialized data are available at the differential CML outputs to drive either an optical transmitter, coaxial media,
or circuit board/backplane. The transmitter’s CML output buffer is terminated on-chip by 86 to optimize the data
eye as well as to reduce the number of discrete components required. The differential output swing reaches a max-
imum of 1.2 VPP in the normal amplitude mode. A half amplitude mode can be selected via conguration register bit
HAMP_xx. Half amplitude mode can be used to reduce power dissipation when the transmission medium has min-
imal attenuation or for testing of the integrity (loss) of the physical medium
A programmable preemphasis circuit is provided to boost the high frequencies in the transmit data signal to maxi-
mize the data eye opening at the far-end receiver. Preemphasis is particularly useful when the data are transmitted
over backplanes or low-quality coax cables which have a frequency-dependent amplitude loss. For example, for
FR4 material at 2.5 GHz, the attenuation compared to the 1.0 GHz value is about 3 dB. The attenuation is a result
of skin effect loss of the PCB conductor and the dielectric loss of the PCB substrate. This attenuation causes inter-
symbol interface which results in the closing of the data eye at the receiver.
Since this effect is predictable for a given type of PCB material, it is possible to compensate for this effect in two
ways - transmitter preemphasis and receiver equalization. Each of these techniques boosts the high frequency
components of the signal but transmit preemphasis is preferred due to the ease of implementation and the better
power utilization. It also gives a better signal-to-noise ratio because receiver equalization amplies both the signal
and the noise at the receiver
.....
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LDIN[7:0]
.....
XCK311
.....
HDOUTx
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p
2
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p
0
p
7
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6
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4
LATENCY
相關(guān)PDF資料
PDF描述
M-ORT82G51BM680-DB FPGA, 1296 CLBS, 333000 GATES, PBGA680
M-ORT82G52BM680-DB FPGA, 1296 CLBS, 333000 GATES, PBGA680
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