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| 型號： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 73/123頁 |
| 文件大小： | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
53
Cell Mode Receive Path
The receive logic blocks unique to the cell mode are shown in Figure 39 and are described in the next sections.
Prior to reaching this logic the received data has been demultiplexed, frame aligned and descrambled by the SER-
DES and SONET logic and is formatted on a per channel basis as 32-bit words with an accompanying clock. The
clock is a 77.76 MHz clock provided by the DEMUX block performing a divide-by-4 operation on RWCKxx.
The Data Extractor and receive FIFO (RXFIFO) process the data on a per channel basis. The receive FIFO also
performs a clock domain transfer to the 156 MHz domain of the Input Port Controller (IPC2/8) blocks. The IPC2/8
blocks perform the two-link or eight-link alignment functions. In two-link alignment mode, the received data are
passed to the FPGA logic as 40-bit words at the 156 MHz rate. In eight-link alignment mode, the received data are
passed to the FPGA logic as a single 160-bit word, again at the 156 MHz rate. Additional mode-dependent status
information is also provided across the Core/FPGA interface.
Figure 39. Receive Path Logic Unique to Cell Mode
RX FIFO Data from Other Channel
Cell
Extractor
RX
FIFO
Write
IPC2
Control
FIFO
Read
Control
or
IPC8
Block
in Two-Link Alignment Group
RX FIFO Data from Other
Channels in Eight-Link
Alignment Group
IPC2_[A:B][1:2]
or IPC8
SYSCLK156[A:B][1:2]
or SYSCLK156 8
6
32
77.76 MHz
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