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| 型號： | M-ORSO82G52BM680-DB |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1296 CLBS, 333000 GATES, PBGA680 |
| 封裝： | PLASTIC, FBGA-680 |
| 文件頁數(shù)： | 101/123頁 |
| 文件大?。?/td> | 2207K |
| 代理商： | M-ORSO82G52BM680-DB |
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Lattice Semiconductor
ORCA ORSO82G5 Data Sheet
79
Table 20. Per-Channel Status Register Descriptions (continued)
(0x) Abso-
lute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
30809 - AA
30819 - AB
30829 - AC
30839 - AD
30909 - BA
30919 - BB
30929 - BC
30939 - BD
[0]
RSVD
00
Reserved
[1]
OOF_xx
OOF_xx = 1 indicates OOF has been detected
in this link. If the corresponding alarm enable
bit has been set, a 1 on this bit will cause an
alarm
Both
[2]
EX_SEQ_ERR_xx
Excessive Sequence Errors, EX_SEQ_ERR =
1 indicates that three consecutive cells contain-
ing sequence errors have been detected in this
link. If the corresponding alarm enable bit has
been set, a 1 on this bit will cause an alarm.
Cell
[3]
SEQ_ERR_xx
Sequence Error, SEQ_ERR = 1 indicates that a
sequence error has been detected for a cell on
this link. If the corresponding alarm enable bit
has been set, a 1 on this bit will cause an
alarm.
Cell
]4]
CELL_BIP_ERR_xx
Cell Mode BIP Error, CELL_BIP_ERR = 1 indi-
cates that a BIP error has been detected in a
cell on the link. If the corresponding alarm
enable bit has been set, a 1 on this bit will
cause an alarm.
Cell
[5]
B1_ERR_xx
Bit Interleaved Parity Error, B1_ERR = 1 indi-
cates that a Section B1 error has been
detected on the link.If the corresponding alarm
enable bit has been set, a 1 on this bit will
cause an alarm.
Both
[6]
RX_FIFO_OVRUN_xx
Receive FIFO Overrun, RX_FIFO_OVRUN_xx
= 1 indicates that the asynchronous RX FIFO
has detected an overrun condition. If the corre-
sponding alarm enable bit has been set, a 1 on
this bit will cause an alarm.
Cell
[7]
RDI_xx
Remote Defect Indication, RDI = 1 indicates
that a RDI has been detected on the link. If the
corresponding alarm enable bit has been set, a
1 on this bit will cause an alarm
Both
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