參數(shù)資料
型號: LTC3850EUF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 0.1 A DUAL SWITCHING CONTROLLER, 860 kHz SWITCHING FREQ-MAX, PQCC28
封裝: 4 X 4 MM, PLASTIC, QFN-28
文件頁數(shù): 14/32頁
文件大?。?/td> 474K
代理商: LTC3850EUF
LTC3850
21
3850f
relationship between the voltage on the FREQ/PLLFLTR
pin and operating frequency is shown in Figure 8 and
specied in the Electrical Characteristics table. Note that
the LTC3850 can only be synchronized to an external clock
whose frequency is within range of the LTC3850’s internal
VCO. This is guaranteed to be between 250kHz and 780kHz.
A simplied block diagram is shown in Figure 9.
If the external clock frequency is greater than the internal
oscillator’s frequency, fOSC, then current is sourced con-
tinuously from the phase detector output, pulling up the
FREQ/PLLFLTR pin. When the external clock frequency is
less than fOSC, current is sunk continuously, pulling down
the FREQ/PLLFLTR pin. If the external and internal frequen-
cies are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to the
phase difference. The voltage on the FREQ/PLLFLTR pin is
adjusted until the phase and frequency of the internal and
external oscillators are identical. At the stable operating
point, the phase detector output is high impedance and
the lter capacitor CLP holds the voltage.
The loop lter components, CLP and RLP, smooth out the
current pulses from the phase detector and provide a
stable input to the voltage-controlled oscillator. The lter
components CLP and RLP determine how fast the loop
acquires lock. Typically RLP = 10k and CLP is 2200pF to
0.01F.
Typically, the external clock (on MODE/PLLIN pin)
input high threshold is 1.6V, while the input low thres-
hold is 1.2V.
Minimum On-Time Considerations
Minimum on-time tON(MIN) is the smallest time duration
that the LTC3850 is capable of turning on the top MOSFET.
It is determined by internal timing delays and the gate
charge required to turn on the top MOSFET. Low duty
cycle applications may approach this minimum on-time
limit and care should be taken to ensure that
t
V
ON MIN
OUT
IN
()
<
f
If the duty cycle falls below what can be accommodated
by the minimum on-time, the controller will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple voltage and current will increase.
The minimum on-time for the LTC3850 is approximately
90ns. However, as the peak sense voltage decreases the
minimum on-time gradually increases to 130ns. This is
of particular concern in forced continuous applications
with low ripple current at light loads. If the duty cycle
drops below the minimum on-time limit in this situation,
a signicant amount of cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
DIGITAL
PHASE/
FREQUENCY
DETECTOR
VCO
2.4V
RLP
CLP
3850 F09
FREQ/
PLLFLTR
EXTERNAL
OSCILLATOR
MODE/
PLLIN
Figure 9. Phase-Locked Loop Block Diagram
APPLICATIONS INFORMATION
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