參數(shù)資料
型號: LTC3850EUF
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: 0.1 A DUAL SWITCHING CONTROLLER, 860 kHz SWITCHING FREQ-MAX, PQCC28
封裝: 4 X 4 MM, PLASTIC, QFN-28
文件頁數(shù): 13/32頁
文件大小: 474K
代理商: LTC3850EUF
LTC3850
20
3850f
Setting Output Voltage
The LTC3850 output voltages are each set by an external
feedback resistive divider carefully placed across the
output, as shown in Figure 7. The regulated output volt-
age is determined by:
VV
R
OUT
B
A
=+
08
1
.
To improve the frequency response, a feed-forward ca-
pacitor, CFF, may be used. Great care should be taken to
route the VFB line away from noise sources, such as the
inductor or the SW line.
skipping in order to limit the short-circuit current. In this
situation the bottom MOSFET will be dissipating most of
the power but less than in normal operation. The short-
circuit ripple current is determined by the minimum on-
time tON(MIN) of the LTC3850 (≈ 90ns), the input voltage
and inductor value:
It
V
L
LSC
ON MIN
IN
()
(
)
=
The resulting short-circuit current is:
I
V
R
I
SC
SENSE MAX
SENSE
LSC
=
13
1
2
/
()
Phase-Locked Loop and Frequency Synchronization
The LTC3850 has a phase-locked loop (PLL) comprised of
an internal voltage-controlled oscillator (VCO) and a phase
detector. This allows the turn-on of the top MOSFET of
controller 1 to be locked to the rising edge of an external
clock signal applied to the MODE/PLLIN pin. The turn-on
of controller 2’s top MOSFET is thus 180 degrees out-
of-phase with the external clock. The phase detector is
an edge sensitive digital type that provides zero degrees
phase shift between the external and internal oscillators.
This type of phase detector does not exhibit false lock to
harmonics of the external clock.
The output of the phase detector is a pair of complemen-
tary current sources that charge or discharge the external
lter network connected to the FREQ/PLLFLTR pin. The
Fault Conditions: Current Limit and Current Foldback
The LTC3850 includes current foldback to help limit load
current when the output is shorted to ground. If the out-
put falls below 50% of its nominal output level, then the
maximum sense voltage is progressively lowered from its
maximum programmed value to one-third of the maximum
value. Foldback current limiting is disabled during the
soft-start or tracking up. Under short-circuit conditions
with very low duty cycles, the LTC3850 will begin cycle
FREQ/PLLFLTR PIN VOLTAGE (V)
0
FREQUENCY
(kHz)
0.5
1
1.5
2
3850 F08
2.5
0
100
300
400
500
900
800
700
200
600
1/2 LTC3850
VFB
VOUT
RB
CFF
RA
3850 F07
Figure 8. Relationship Between Oscillator Frequency
and Voltage at the FREQ/PLLFLTR Pin
Figure 7. Setting Output Voltage
APPLICATIONS INFORMATION
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