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參數(shù)資料
| 型號： | LTC2450IDC-1#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 3/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG 6-DFN |
| 產(chǎn)品培訓(xùn)模塊： | LTC2460 and LTC2450 Delta Sigma ADC Families |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 30 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.05mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 6-DFN-EP（2x2） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 其它名稱： | LTC2450IDC-1#TRMPBFDKR |
LTC2450-1
11
24501fc
Examples of Aborting Cycle using CS
For some applications the user may wish to abort the I/O
cycle and begin a new conversion. If the LTC2450-1 is in
the data output state, a CS rising edge clears the remaining
data bits from memory, aborts the output cycle and triggers
a new conversion. Figure 9 shows an example of aborting
an I/O with idle-high (CPOL = 1) and Figure 10 shows an
example of aborting an I/O with idle-low (CPOL = 0).
A new conversion cycle can be triggered using the CS
signal without having to generate any serial clock pulses
as shown in Figure 11. If SCK is maintained at a LOW
logic level, after the end of a conversion cycle, a new
conversion operation can be triggered by pulling CS low
and then high. When CS is pulled low (CS = LOW), SDO
will output the most signicant bit (D15) of the result of
the just completed conversion. While a low logic level is
maintained at SCK pin and CS is subsequently pulled high
(CS = HIGH) the remaining 15 bits of the result (D14:D0)
are discarded and a new conversion cycle starts.
Following the aborted I/O, additional clock pulses in the
CONVERT state are acceptable, but excessive signal tran-
sitions on SCK can potentially create noise on the ADC
during the conversion, and thus may negatively inuence
the conversion accuracy.
APPLICATIONS INFORMATION
Figure 8. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge Triggers a New Conversion
Figure 7. Idle-Low (CPOL = 0) Clock. CS Triggers a New Conversion
D15
D14
D13
D12
D2
D1
D0
clk1
clk2
clk3
clk4 clk14
clk15
clk16
SCK
SD0
CONVERT
SLEEP
LOW ICC
DATA OUTPUT
24501 F07
CS
D15
D14
D13
D12
D2
D1
D0
SD0
clk1
clk2
clk3
clk4
clk15
clk14
clk16
SCK
CONVERT
SLEEP
LOW ICC
DATA OUTPUT
24501 F08
CS
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