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參數(shù)資料
| 型號： | LTC2450IDC-1#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG 6-DFN |
| 產(chǎn)品培訓(xùn)模塊： | LTC2460 and LTC2450 Delta Sigma ADC Families |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 30 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.05mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 6-DFN-EP（2x2） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 產(chǎn)品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 其它名稱： | LTC2450IDC-1#TRMPBFDKR |
LTC2450-1
8
24501fc
APPLICATIONS INFORMATION
Input Voltage Range
The ADC is capable of digitizing true rail-to-rail input sig-
nals. Ignoring offset and full-scale errors, the converter
will theoretically output an “all zero” digital result when
the input is at ground (a zero scale input) and an “all
one” digital result when the input is at VCC (a full-scale
input). In an under-range condition, for all input voltages
less than the voltage corresponding to output code 0, the
converter will generate the output code 0. In an over-range
condition, for all input voltages greater than the voltage
corresponding to output code 65535 the converter will
generate the output code 65535.
Output Data Format
The LTC2450-1 generates a 16-bit direct binary encoded
result. It is provided, MSB rst, as a 16-bit serial stream
through the SDO output pin under the control of the SCK
input pin (see Figure 3).
During the data output operation the CS input pin must
be pulled low (CS = LOW). The data output process starts
with the most signicant bit of the result being present
at the SDO output pin (SDO = D15) once CS goes low.
A new data bit appears at the SDO output pin following
every falling edge detected at the SCK input pin. The
output data can be reliably latched by the user using the
rising edge of SCK.
Ease of Use
The LTC2450-1 data output has no latency, lter settling
delay or redundant results associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog input voltages requires no special ac-
tions.
The LTC2450-1 includes a proprietary input sampling
scheme that reduces the average input current several
orders of magnitude as compared to traditional delta
sigma architectures. This allows external lter networks
to interface directly to the LTC2450-1. Since the average
input sampling current is 50nA, an external RC lowpass
lter using a 1k
Ω and 0.1μF results in <1LSB error.
Reference Voltage Range
The converter uses the power supply voltage (VCC) as the
positive reference voltage (see Figure 1). Thus, the refer-
ence range is the same as the power supply range, which
extends from 2.7V to 5.5V. The LTC2450-1’s internal noise
level is extremely low so the output peak-to-peak noise
remains well below 1LSB for any reference voltage within
this range. Thus the converter resolution remains at 1LSB
independent of the reference voltage. INL, offset, and full-
scale errors vary with the reference voltage as indicated
by the Typical Performance Characteristics graphs. These
error terms will decrease with an increase in the reference
voltage (as the LSB size in μV increases).
Figure 3. Data Output Timing
D15
LSB
SDO
SCK
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D0
D1
24501 F03
t1
t3
tKQ
tlSCK
thSCK
t2
CS
MSB
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