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參數(shù)資料
| 型號： | LTC2450IDC-1#TRMPBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 20/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT DELTA SIG 6-DFN |
| 產品培訓模塊： | LTC2460 and LTC2450 Delta Sigma ADC Families |
| 標準包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 30 |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.05mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 6-WFDFN 裸露焊盤 |
| 供應商設備封裝： | 6-DFN-EP（2x2） |
| 包裝： | 標準包裝 |
| 輸入數(shù)目和類型： | 1 個單端，單極 |
| 產品目錄頁面： | 1348 (CN2011-ZH PDF) |
| 其它名稱： | LTC2450IDC-1#TRMPBFDKR |
LTC2450-1
9
24501fc
Conversion Status Monitor
For certain applications, the user may wish to monitor
the LTC2450-1 conversion status. This can be achieved
by holding SCK HIGH during the conversion cycle. In
this condition, whenever the CS input pin is pulled low
(CS = LOW), the SDO output pin will provide an indication
of the conversion status. SDO = HIGH is an indication of
a conversion cycle in progress while SDO = LOW is an
indication of a completed conversion cycle. An example
of such a sequence is shown in Figure 4.
Conversionstatusmonitoring,whilepossible,isnotrequired
for LTC2450-1 as its conversion time is xed and equal at
approximately 16.6ms (21ms maximum). Therefore, ex-
ternal timing can be used to determine the completion of a
conversion cycle.
SERIAL INTERFACE
The LTC2450-1 transmits the conversion result and receives
the start of conversion command through a synchronous
3-wire interface. This interface can be used during the
CONVERT and SLEEP states to assess the conversion
status and during the DATA OUTPUT state to read the
conversion result, and to trigger a new conversion.
APPLICATIONS INFORMATION
Serial Interface Operation Modes
The following are a few of the more common interface
operation examples. Many more valid control and serial
data output operation sequences can be constructed based
upon the above description of the function of the three
digital interface pins.
The modes of operation can be summarized as follows:
1) The LTC2450-1 functions with SCK idle high (commonly
known as CPOL = 1) or idle low (commonly known as
CPOL = 0).
2) After the 16th bit is read, the user can choose one of
two ways to begin a new conversion. First, one can
pull CS high (CS =
↑). Second, one can use a high-low
transition on SCK (SCK =
↓).
3) At any time during the Data Output state, pulling CS
high (CS =
↑) causes the part to leave the I/O state,
abort the output and begin a new conversion.
4) When SCK = HIGH, it is possible to monitor the conver-
sion status by pulling CS low and watching for SDO
to go low. This feature is available only in the idle-high
(CPOL = 1) mode.
Figure 4. Conversion Status Monitoring Mode
SLEEP
t1
t2
SDO
SCK = HI
CONVERT
24501 F04
CS
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