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參數(shù)資料
| 型號： | LTC1196 |
| 廠商： | Linear Technology Corporation |
| 英文描述： | 8-Bit, SO-8,1MSPS ADCs(SO-8封裝，8位，1MSPS，模數(shù)轉(zhuǎn)換器（差分輸入）) |
| 中文描述： | 8位，SO - 8封裝，1MSPS模數(shù)轉(zhuǎn)換器（以SO - 8封裝，8位，1MSPS，模數(shù)轉(zhuǎn)換器（差分輸入）） |
| 文件頁數(shù)： | 23/28頁 |
| 文件大?。?/td> | 373K |
| 代理商： | LTC1196 |
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LTC1196/LTC1198
U
S
A
3V VERSUS 5V PERFORMANCE COMPARISON
Table 1 shows the performance comparison between 3V
and 5V supplies. The power dissipation drops by a factor
of five when the supply is reduced to 3V. The converter
slows down somewhat but still gives excellent perfor-
mance on a 3V rail. With a 3V supply, the LTC1196
converts in 1.6
μ
s, samples at 450kHz, and provides a
500kHz linear-input bandwidth.
Dynamic accuracy is excellent on both 5V and 3V. The
ADCs typically provide 49.3dB of 7.9 ENOBs of dynamic
accuracy at both 3V and 5V. The noise floor is extremely
low, corresponding to a transition noise of less than
0.1LSB. DC accuracy includes
±
0.5LSB total unadjusted
error at 5V. At 3V, linearity error is
±
0.5LSB while total
unadjusted error increases to
±
1LSB.
O
PPLICATI
IU
U
Table 1. 5V/3V Performance Comparison
LTC1196-1
P
DISS
Max f
SMPL
Min t
CONV
INL (Max)
Typical ENOBs
Linear Input Bandwidth (ENOBs > 7)
LTC1198-1
P
DISS
P
DISS
(Shutdown)
Max f
SMPL
Min t
CONV
INL (Max)
Typical ENOBs
Linear Input Bandwidth (ENOBs > 7)
5V
3V
50mW
1MHz
600ns
0.5LSB
7.9 at 300kHz
1MHz
10mW
383kHz
1.6
μ
s
0.5LSB
7.9 at 100kHz
500kHz
50mW
15
μ
W
750kHz
600ns
0.5LSB
7.9 at 300kHz
1MHz
10mW
9
μ
W
287kHz
1.6
μ
s
0.5LSB
7.9 at 100kHz
500kHz
U
S
A
O
PPLICATI
TYPICAL
PLD Interface Using the Altera EPM5064
The Altera EPM5064 has been chosen to demonstrate the
interface between the LTC1196 and a PLD. The EPM5064
is programmed to be a 12-bit counter and an equivalent
74HC595 8-bit shift register as shown in Figure 12. The
circuit works as follows: bringing ENA high makes the CS
output high and the EN input low to reset the LTC1196 and
disable the shift register. Bringing ENA low, the CS output
goes high for one CLK cycle with every 12 CLK cycles. The
inverted signal, EN, of the CS output makes the 8-bit data
available on the B0-B7] lines. Figures 13 and 14 show the
interconnection between the LTC1196 and EPM5064 and
the timing diagram of the signals between these two
devices. The CLK frequency in this circuit can run up to
f
CLK(MAX)
of the LTC1196.
1196/98 F12
DATA
CLK
12-BIT
CONVERTER
CS
ENA
EN
CLK
B0-B7
8-BIT
SHIFT REGISTER
CS
ENA
CLK
DATA
B0-B7
Figure 12. An Equivalent Circuit of the EPM5064
Figure 13. Intefacing the LTC1196 to the Altera EPM5064 PLD
3, 14, 25, 36
EPM5064
CLK
33
23
34
35
1196/98 F13
V
CC
+
–
DATA
1
37
38
39
40
41
42
44
9-13, 21,
31, 32, 43
CLK
B7
B0
ENA
–IN
GND
V
CC
CLK
D
OUT
+IN
CS
1
2
3
4
8
7
6
5
LTC1196
V
REF
1
μ
F
RESERVE PINS OF EPM5064:
2, 4-8,15-20, 22, 24, 26-30
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC1196_1 | 制造商:LINER 制造商全稱:Linear Technology 功能描述:8-Bit, SO-8, 1Msps ADCs with Auto-Shutdown Options |
| LTC1196-1AC | 制造商:LINER 制造商全稱:Linear Technology 功能描述:8-Bit, SO-8, 1MSPS ADCs with Auto-Shutdown Options |
| LTC11961ACS8 | 制造商:Linear Technology 功能描述: |
| LTC1196-1ACS8 | 功能描述:IC A/DCONV 8BIT 1MHZ SAMPL 8SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
| LTC1196-1ACS8#PBF | 功能描述:IC A/DCONV 8BIT 1MHZ SAMPL 8SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
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