參數(shù)資料
型號: LTC1196
廠商: Linear Technology Corporation
英文描述: 8-Bit, SO-8,1MSPS ADCs(SO-8封裝,8位,1MSPS,模數(shù)轉(zhuǎn)換器(差分輸入))
中文描述: 8位,SO - 8封裝,1MSPS模數(shù)轉(zhuǎn)換器(以SO - 8封裝,8位,1MSPS,模數(shù)轉(zhuǎn)換器(差分輸入))
文件頁數(shù): 17/28頁
文件大小: 373K
代理商: LTC1196
17
LTC1196/LTC1198
U
S
A
O
PPLICATI
U
U
Figure 4. LTC1198 Operation with D
IN
and D
OUT
Tied Together
SAMPLE RATE (Hz)
0.01
S
0.1
1
10
100
10k
100k
1196/98 F05
0.001
1k
1M
LT1196 V
CC
= 5V
LT1196 V
CC
= 2.7V
LT1198 V
CC
= 5V
LT1198 V
CC
= 2.7V
Figure 5. Supply Current
vs Sample Rate for LTC1196/
LTC1198 Operating on 5V and 2.7V Supplies
Minimize CS Low Time (LTC1198)
In systems that have significant time between conver-
sions, lowest power drain will occur with the minimum CS
low time. Bringing CS low, transfering data as quickly as
possible, then bringing it back high will result in the lowest
current drain. This minimizes the amount of time the
device draws power.
OPERATING ON OTHER THAN 5V SUPPLIES
The LTC1196/LTC1198 operate from single 2.7V to 6V
supplies. To operate the LTC1196/LTC1198 on other than
5V supplies, a few things must be kept in mind.
Input Logic Levels
The input logic levels of CS, CLK and D
IN
are made to
meet TTL on 5V supply. When the supply voltage varies,
the input logic levels also change (see typical curve of
Digital Input Logic Threshold vs Supply Voltage). For
these two ADCs to sample and convert correctly, the
digital inputs have to be in the logical low and high relative
to the operating supply voltage. If achieving micropower
consumption is desirable on the LTC1198, the digital
inputs must go rail-to-rail between supply voltage and
ground (see Reducing Power Consumption section).
When the CS pin is high (= supply voltage), the LTC1198
is in shutdown mode and draws only leakage current. The
status of the D
IN
and CLK input has no effect on the supply
current during this time. There is no need to stop D
IN
and
CLK with CS = high; they can continue to run without
drawing current.
1
2
3
4
CLK
DATA (D
IN
/D
OUT
)
START
SGL/DIFF
ODD/SIGN
DUMMY
B7
B6
DUMMY BITS LATCHED
BY LTC1198
LTC1198 CONTROLS DATA LINE AND SENDS
A/D RESULT BACK TO THE DIGITAL SYSTEM
LTC1198 TAKES CONTROL OF
DATA LINE ON 5TH FALLING CLK
THE DIGITAL SYSTEM CONTROLS DATA LINE
AND SENDS MUX ADDRESS TO LTC1198
THE DIGITAL SYSTEM MUST RELEASE
DATA LINE AFTER 5TH RISING CLK
AND BEFORE THE 5TH FALLING CLK
CS
1196/98 F04
5
DUMMY
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參數(shù)描述
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