參數資料
型號: LTC1196
廠商: Linear Technology Corporation
英文描述: 8-Bit, SO-8,1MSPS ADCs(SO-8封裝,8位,1MSPS,模數轉換器(差分輸入))
中文描述: 8位,SO - 8封裝,1MSPS模數轉換器(以SO - 8封裝,8位,1MSPS,模數轉換器(差分輸入))
文件頁數: 19/28頁
文件大?。?/td> 373K
代理商: LTC1196
19
LTC1196/LTC1198
U
S
A
O
PPLICATI
U
U
CLK. V
ERROR
is proportional to f(“–”) and inversely pro-
portional to f
CLK
. For a 60Hz signal on the “–” input to
generate a 1/4LSB error (5mV) with the converter running
at CLK = 12MHz, its peak value would have to be 18.7V.
ANALOG INPUTS
Because of the capacitive redistribution A/D conversion
techniques used, the analog inputs of the LTC1196/
LTC1198 have one capacitive switching input current
spike per conversion. These current spikes settle quickly
and do not cause a problem. However, if source resis-
tances larger than 100
are used or if slow settling op
amps drive the inputs, care must be taken to insure that the
transients caused by the current spikes settle completely
before the conversion begins.
“+” Input Settling
The input capacitor of the LTC1196 is switched onto “+”
input at the end of the conversion and samples the input
signal until the conversion begins (see Figure 1). The input
capacitor of the LTC1198 is switched onto “+” input during
the sample phase (t
SMPL
, see Figure 7). The sample phase
is 2.5 CLK cycles before conversion starts. The voltage on
the “+” input must settle completely within t
SMPL
for the
LTC1196/LTC1198. Minimizing R
SOURCE+
will improve
the input settling time. If a large “+” input source resis-
tance must be used, the sample time can be increased by
allowing more time between conversions for the LTC1196
or by using a slower CLK frequency for the LTC1198.
Figure 7. LTC1198 “+” and “–” Input Settling Windows
CLK
D
IN
D
OUT
“+” INPUT
“–” INPUT
SAMPLE
HOLD
“+” INPUT MUST
SETTLE DURING
THIS TIME
t
SMPL
t
CONV
CS
START
SGL/DIFF
DUMMY
DON’T CARE
1ST BIT TEST “–” INPUT MUST
SETTLE DURING THIS TIME
B7
1196/98 F07
ODD/SIGN
DUMMY
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相關代理商/技術參數
參數描述
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