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參數(shù)資料
| 型號： | LM4560 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Advanced PCI Audio Accelerator |
| 中文描述： | 先進的PCI音頻加速器 |
| 文件頁數(shù)： | 51/54頁 |
| 文件大小： | 380K |
| 代理商： | LM4560 |
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4.0 Functional Description
(Continued)
Present
State
D0
D2 or
D1
Next
State
D1
D0
State Change Way
HIFW
HIFW
Present
State
D0
D2
D0
Next
State
D2
D3
D3
State Change Way
HIFW
HIFW or Inactivity Timer expires
HIFW
5.1.2 Timing
The timing descriptions of host interface signals. All signal’s transition edges are respected to the rising edge of PCICLK. The
setup time and hold time requirements are illustrated in Figure 4
5.1.2.1 Slave Read/Write Timing
Slave read/write means that host performs I/O read/write operation to audio block while audio block acts as a bus slave. Data
transition occurs at the rising edge of PCICLK while both chip select signal and DATARDY are active. They are two-clock wait
states from chip select signal and DATARDY.
Timing diagram are printed into file: sl_io_rd.ps and sl_io_wr.ps .
5.1.2.2 Master Read/Write
There’s one clock wait state of IRDY which means: 1) IRDY can be asserted in 2 clocks after FRAME is asserted; 2) IRDY has
to be de-asserted for 1 clock after each of data transferring.
Timing
diagram
are
printed
into
file:
ma_mem_rd1.ps,
ma_mem_wr3.ps.
ma_memrd2.ps,
ma_mem_rd3.ps,
ma_mem_wr2.ps
and
DS100910-5
FIGURE 4. Setup Time and Hold Time of All Signals
www.national.com
51
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