參數(shù)資料
型號(hào)： LM4560
廠商： National Semiconductor Corporation
英文描述： Advanced PCI Audio Accelerator
中文描述： 先進(jìn)的PCI音頻加速器
文件頁(yè)數(shù)： 49/54頁(yè)
文件大小： 380K
代理商： LM4560
4.0 Functional Description
(Continued)
Read/Write
Bit
7..1
Bit 0
reserved
0
1
AGC disable
AGC enable
MX44 Treble Left Control
Default 80h
Read/Write
Bit 7..4 16 level treble left control
Bit 3..0 reserved
MX45 Treble Right Control
Default 80h
Read/Write
Bit 7..4 16 level treble right control
Bit 3..0 reserved
MX46 Bass Left Control
Default 80h
Read/Write
Bit 7..4 16 level bass left control
Bit 3..0 reserved
MX47 Bass Right Control
Default 80h
Read/Write
Bit 7..4 16 level bass right control
Bit 3..0 reserved
4.2.1.21 SB16 Configuration/Status Register
MX80 Sound Blaster Interrupt Setup Register
Default 00h
Read/Write
Bit
7..6
Bit 5
reserved (read as 1)
1
IRQ12 is used as legacy SB interrupt
line
IRQ11 is used as legacy SB interrupt
line
IRQ10 is used as legacy SB interrupt
line
IRQ7 is used as legacy SB interrupt
line
IRQ5 is used as legacy SB interrupt
line
IRQ9 is used as legacy SB interrupt
line
Only 1 bit of this register can be set 1 at any one time
Content of this register must be consistent with header 1 in-
terrupt line configuration register.
MX81 Sound Blaster DMA Channel Setup Register
Default 00h
Read/Write
Bit 4
1
Bit 3
1
Bit 2
1
Bit 1
1
Bit 0
1
Bit
7..2
reserved (read as 0)
Bit 1
1
legacy DMA channel 1 is used as
legacy SB DMA channel
legacy DMA channel 0 is used as
legacy SB DMA channel
Bit 0
1
Only 1 bit of this register can be set 1 at any one time
Content of this register must be consistent with CR1 on SB
DMA channel setup.
MX82 Sound Blaster Interrupt Status Register
Default 00h
Read Only
Bit
7..3
Bit 2
Bit 1
reserved
1
1
MPU-401 MIDI interrupt request
Sound Blaster Bx type command DMA
interrupt request
Sound Blaster Non-Bx type command
DMA interrupt request
Bit 0
1
0: no interrupt
1: interrupt triggered
4.2.1.22 Interface With Wave Engine
4.2.1.22.1
Interfaced Register
All registers that physically implemented in wave engine are
addressed using the 3-bit wide address line and 8-bit wide
unidirectional data line initiated by Sound Blaster ESP Emu-
lation Engine. These registers are considered to be the pe-
ripheral registers of implemented SB ESP engine.
4.2.1.22.2
SB ESP DMA Control Register
4.2.1.22.2.1
SBDMPD Direct Mode Playback Data Register
SB ESP Address: 6h
Size: 8 bits
Type: Write Only For SB ESP
Read Only For Wave Engine
Default: 80h
Bit 7..0 Direct Mode Playback Data
Any time after this register has ever been written, a Direct-
ModePlay internal flag will be set by wave engine. This flag
will
be
cleared
when
ESPRESET
LegacyDMARun is active. When this flag is active, the un-
signed 8 bit PCM data will be output to AC-97 Codec.
4.2.1.22.2.2
SBE2R DMA Testing Byte Register
SB ESP Address: 7h
Size: 8 bits
Type: Write Only For SB ESP
Read Only For Wave Engine
Default: 00h
Bit 7..0 testing byte that will be transferred to system location
specified by DMAR0–3.
After this register has ever been written, E2Status (source
from wave engine) will be set high. E2Status will be cleared
after the testing byte has been sent to the system location.
4.2.1.22.2.3
SBDMAC SB DMA Current Block Length Low
Byte
SB ESP Address: 0h
Size: 8 bits
Type: Write Only For SB ESP
Read Only For Wave Engine
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active
or
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