參數(shù)資料
型號(hào)： LM4560
廠商： National Semiconductor Corporation
英文描述： Advanced PCI Audio Accelerator
中文描述： 先進(jìn)的PCI音頻加速器
文件頁(yè)數(shù)： 33/54頁(yè)
文件大?。?/td> 380K
代理商： LM4560
4.0 Functional Description
(Continued)
Channels which don’t require PCI bus cycle, i.e. cache hit
channels and I2StoMIX channel, have lower priority.
Channels which depend on other channel’s result, i.e.
Main Mixer Capture channel, Chorus Send channel and
Reverb Send channel, have the lowest priority.
Basically, all operation of one channel include address generation, data reading/writing, interpolation, per channel LFO, low fre-
quency FM/AM, Envelope calculation, PAN, volume adjusting and mixer accumulation. We call it Channel Operation. After all
channel’s operation are done, the mixing result will be sent to FIFO. We call this Mixing Loop.
Before each Mixing Loop, Scheduler scans cache hit/miss flags of all active channels to decide the processing sequence of the
current Loop.
4.1.2 Address Engine
Address generation, data reading/writing, per channel LFO, low frequency FM and interpolation coefficient calculation are pro-
cessed by Address Engine.
Terms:
CCI (6 bits)— Current Channel Index
CPTR (1 bit)— Cache Pointer
ESO (16 bits)— Ending Sample Offset (relative to loop begin sample)
CSO (16 bits)— Current Sample Offset (relative to loop begin sample)
CSO_SIGN (1 bit)— Sign bit of CSO
CAO (18 bits) — Current Address Offset (relative to loop begin address)
LBA (32 bits)— Loop Begin Address
CSA (32 bits)— Current Sample Address
FMS (4 bits)— Frequency Modulation Step
FMC (2 bit)— Frequency Modulation Control
SIN (4 bits)— current state of sin counter
FMA (8 bits)— Frequency Modulation Amount
BL (2 bits)— Burst read Length
DELTA (15 bits)— Sample increment number per 48 kHz clock (format 3.12)
ALPHA (12 bits)— Interpolation coefficient, i.e. fractional part of CSO
NEWCSO (16 bits)— the next CSO
NEWALPHA (12 bits)— the next ALPHA
The procedure of address engine is described as following:
(1) Load RegE0h // read FMS, CSO, ALPHA from ARAM
Load RegE4h // read LBA from ARAM
if (8 bit && MONO) CAO = CSO;
else if (16 bit && STEREO) CAO = CSO
<<
2;
else CAO = CSO
<<
1;
FMA = SIN*FMS;
(3) Load RegE8h // read ESO, DELTA, CPTR from ARAM
if(Cache miss)
{ // calculate address CSA = LBA + (CSO_SIGN==0) CAO : CAO; // 32 bit addition }
BL is decided by CSA[1:0] and data_type[2:1];
(data_type[2:0] refers to bit[15:13] of channel register F0h)
BL
CSA[1:0]=00
1
1
1
2
CSA[1:0]=01
1
2
2
3
CSA[1:0]=10
1
2
2
3
CSA[1:0]=11
2
2
2
3
Data_type[2:1]=00
Data_type[2:1]=01
Data_type[2:1]=10
Data_type[2:1]=11
BL (Burst Length)
Update RegE8h with new CPTR
Update RegECh with new LFO_CTRL & LFO_CT
www.national.com
33
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