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參數(shù)資料
| 型號： | LM4560 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Advanced PCI Audio Accelerator |
| 中文描述： | 先進的PCI音頻加速器 |
| 文件頁數(shù)： | 37/54頁 |
| 文件大?。?/td> | 380K |
| 代理商： | LM4560 |
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4.0 Functional Description
(Continued)
SIN[3:0]
B
A
9
8
7
6
5
4
3
2
1
SIN_S
1
1
1
1
1
1
1
1
1
1
1
One cycle of SIN counter
4.1.7 Recording
A down sampling SRC is used for recording.
4.1.8 PCI Buffer/Sample Cache
PCI Buffer (or called Sample Cache) is a 128x32 bit SRAM which is designed to reduce consumption of PCI bus bandwidth. Each
wave channel has two double words of buffer. The playback channel uses it as a pre-fetch buffer, while the recording channel
uses it as a post-write buffer.
4.1.9 CODEC Buffer/Sample FIFO
Between the Wave Engine and the CODEC, there’s another SRAM (128x20 bit) called the CODEC Buffer (or the Sample FIFO)
which is for synchronization between wave engine and serial interface for optimization of PCI bus utilization.
This 128-word CODEC buffer is partitioned into several sections:
Section
Size
Address
Description
PLAYBACK
PCM_L Out FIFO
PCM_R Out FIFO
SURR_L Out FIFO
SURR_R Out FIFO
CENTER Out FIFO
LFE Out FIFO
LINE1 Out FIFO
LINE2 Out FIFO
HSET Out FIFO
I2S_L Out Buffer
I2S_R Out Buffer
SPDIF_L Out Buffer
SPDIF_R Out Buffer
RECORDING
PCM_L In Buffer
PCM_R In Buffer
LINE1 In Buffer
LINE2 In Buffer
MIC In Buffer
HSET In Buffer
REVERB_L SEND Buffer
REVERB_R SEND Buffer
CHORUS_L SEND Buffer
CHORUS_R SEND Buffer
PCM Left Playback FIFO
PCM Right Playback FIFO
Surround Left Playback FIFO
Surround Right Playback FIFO
Center Playback FIFO
LFE Playback FIFO
MODEM Line1 Output FIFO
MODEM Line2 Output FIFO
Handset Output FIFO
I2S Left Output Buffer
I2S Right Output Buffer
S/PDIF Left Output Buffer
S/PDIF Right Output Buffer
PCM Left Recording Buffer
PCM Right Recording Buffer
Modem Line1 Input Buffer
Modem Line2 Input Buffer
Microphone Input Buffer
Handset Input Buffer
Reverb Left Send Buffer
Reverb Right Send Buffer
Chorus Left Send Buffer
Chorus Right Send Buffer
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