參數(shù)資料
型號(hào)： LM2633
廠商： National Semiconductor Corporation
英文描述： Advanced Two-Phase Synchronous Triple Regulator Controller for Notebook CPUs
中文描述： 先進(jìn)的兩相同步三穩(wěn)壓控制器用于筆記本處理器
文件頁(yè)數(shù)： 28/40頁(yè)
文件大?。?/td> 1350K
代理商： LM2633
Output Inductor Selection
(Continued)
be a good idea to adjust the inductance value so that a
requirement of 3.2 capacitors can be reduced to 3 capaci-
tors.
Inductor ripple current is often the criterion for selecting an
output inductor. However, in the CPU core or GTL bus
application, it is usually of lower priority. That is partly be-
cause the stringent output ripple voltage requirement auto-
matically limits the inductor ripple current level. It is never-
theless a good idea to double check the ripple current. The
equation is:
(13)
where min(V
in_max
, 17V) means the smaller of V
in_max
and
17V.
What is more important is the ripple content, which is defined
by I
/ I
. Generally speaking, a ripple content of
less than 50% is ok. Too high a ripple content will cause too
much loss in the inductor.
Example: V
in_max
= 21V, V
n
= 1.6V, f = 250kHz, L = 1.7μH.
If the maximum load current is 14A, then the ripple content is
4.3A / 14A = 30%.
When choosing the inductor, the saturation current should
be higher than the maximum peak inductor current. The
RMS current rating should be higher than the maximum load
current.
MOSFET Selection
Bottom FET Selection
During normal operations, the bottom FET is turned on and
off at almost zero voltage. So only conduction loss is present
in the bottom FET. The bottom FET power loss peaks at the
maximum input voltage and load current. The most important
parameter when choosing the bottom FET is the on resis-
tance. The less the on resistance, the less the power loss.
The equation for the maximum allowed on resistance at
room temperature for a given FET package, is:
(14)
where T
j_max
is the maximum allowed junction temperature
in the FET, T
a_max
is the maximum ambient temperature,
R
is the junction-to-ambient thermal resistance of the FET,
and TC is the temperature coefficient of the on resistance
which is typically 4000ppm/C.
If the calculated on resistance is smaller than the lowest
value available, multiple FETs can be used in parallel. If the
design criterion is to use the highest-R
FET, then the
R
ds_max
of each FET can be increased due to reduced
current. In the case of two FETs in parallel, multiply the
calculated on resistance by 4 to obtain the on resistance for
each FET. In the case of three FETs, that number is 9. Since
efficiency is very important in a mobile PC, having the lowest
on resistance is usually more important than fully utilizing the
thermal capacity of the package. So it is probably better to
find the lowest-R
ds
FET first, and then determine how many
are needed.
Example: T
= 100C, T
= 60C, R
θ
ja
= 60C/W,
V
in_max
= 21V, V
n
= 1.6V, and I
load_max
= 10A.
If the lowest-on-resistance FET has a R
of 10m
, then
two can be used in parallel. The temperature rise on each
FET will not go to T
because each FET is now dissipat-
ing only half of the total power.
Alternatively, two 22m
FETs can be used in parallel, with
each FET reaching T
. This may lower the FET cost, but
will double the bottom switch power loss.
Top FET Selection
The top FET has two types of power losses - the switching
loss and the conduction loss. The switching loss mainly
consists of the cross-over loss and the bottom diode reverse
recovery loss. It is rather difficult to estimate the switching
loss. A general starting point is to allot 60% of the top FET
thermal capacity to switching loss. The best way to find out is
still to test it on bench. The equation for calculating the on
resistance of the top FET is thus:
(15)
where T
is the maximum allowed junction temperature
in the FET, T
is the maximum ambient temperature,
R
is the junction-to-ambient thermal resistance of the FET,
and TC is the temperature coefficient of the on resistance
which is typically 4000ppm/C.
Example: T
= 100C, T
a_max
= 60, R
θ
ja
= 60C/W,
V
in_min
= 14V, V
n
= 1.6V, and I
load_max
= 10A.
Since the switching loss usually increases with bigger FETs,
choosing a top FET with a much smaller on resistance
sometimes may not yield noticeable lower temperature rise
and better efficiency.
It is recommended that the peak value of the V
ds
of the top
FET does not exceed 200 mV when the top FET conducts,
otherwise the COMPx pin voltage may reach its high clamp
value (2V) and cause loss of regulation.
L
www.national.com
28
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