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參數(shù)資料
| 型號： | LM2633 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Advanced Two-Phase Synchronous Triple Regulator Controller for Notebook CPUs |
| 中文描述： | 先進(jìn)的兩相同步三穩(wěn)壓控制器用于筆記本處理器 |
| 文件頁數(shù)： | 26/40頁 |
| 文件大?。?/td> | 1350K |
| 代理商： | LM2633 |
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Output Capacitor Selection
(Continued)
Because the response speed of the regulator is slow com-
pared to a typical CPU load transient, the regulator has to
rely heavily on the output capacitors to handle the load
transient. The initial overshoot or undershoot is caused by
the ESR of the output capacitors. How the output voltage
recovers after that initial excursion depends on how fast the
output inductor current ramps and how large the output
capacitance is. See Figure 3 If the total combined ESR of
the output capacitors is not low enough, the initial output
voltage excursion will violate the specification, see
V
. If
the ESR is low enough, but there is not enough output
capacitance, output voltage will have too much an extra
excursion and travel outside the specification window, before
it returns to its nominal value, see
V
c2
.
During a load transient, the delta output voltage
V
has two
changing components. One is the delta voltage across the
ESR (
V
), the other is the delta voltage caused by the
gained charge (
V
). Both delta voltages change with time.
For
V
r
, the equation is:
(1)
and for
V
q
, the equation is:
(2)
The total change in output voltage during such a load tran-
sient is:
V
c
=
V
r
+
V
q
From Figure 4it can be told that
V
c
will reach its peak value
at some point in time and then it is going to decrease. The
larger the output capacitance is, the earlier the peak will
happen. If the capacitance is large enough, the peak will
occur at the beginning of the transient, i.e.,
V
will decrease
monotonically after the transient happens. To find the peak
position, let the derivative of
V
c
go to zero, and the result is:
(3)
(4)
The target is to find the capacitance value that will yield, at
t
, a
V
c
that equals
V
. By plugging t
expression
into the
V
expression and equating the latter to
V
c_s
, the
following formula is obtained:
(5)
Notice it is already assumed the total ESR is no greater than
R
otherwise the term under the square root will be a
negative value.
There are two scenarios when calculating the C
min
. See
Figure 5 One is that R
is equal to R
e_s
so there is abso-
lutely no room for
V
, which means t
= 0s. The other is
that R
is smaller than R
so there is some room for
V
q
,
which means t
is greater than zero. However, it is not
necessary to differentiate between the two scenarios when
figuring out the C
min
by the above formula.
Allowed transient voltage excursion
The allowed output voltage excursion during a load transient
is:
(6)
Example: V
n
= 1.35V,
δ
% = 7.5%,
λ
% = 1.4%, V
rip
= 20mV
Since the ripple voltage is included in the calculation of
V
c_s
, the inductor ripple current should not be included in
the
worst-case
load
current
worst-case load current excursion should be simply
I
c_s
.
excursion.
That
is,
the
20000807
FIGURE 3. Load Transient Spec. Violation
20000808
FIGURE 4. Delta Output Voltage Components
20000813
FIGURE 5. R
e
= R
e_s
vs R
e
<
R
e_s
L
www.national.com
26
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