參數(shù)資料
型號: LH7A400N0F076B5
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: 32-Bit System-on-Chip
封裝: LH7A400N0F000B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT1020-1.html<1<Always Pb-free,;LH7A400N0F076B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT
文件頁數(shù): 7/65頁
文件大?。?/td> 834K
代理商: LH7A400N0F076B5
32-Bit System-on-Chip
LH7A400
Preliminary data sheet
Rev. 01
16 July 2007
7
NXP Semiconductors
C13
E12
G10
B12
B11
D11
B13
B14
C12
A14
B12
A12
D26
D27
D28
D29
D30
D31
Data Bus
LOW
LOW
12 mA
I/O
M16
M15
A0/nWE1
Asynchronous Address Bus
Asynchronous Memory Write Byte Enable 1
Asynchronous Address Bus
Asynchronous Memory Write Byte Enable 2
HIGH:
nWE1
HIGH:
nWE2
HIGH
12 mA
O
N14
M16
A1/nWE2
HIGH
12 mA
O
M13
K16
K15
K14
J8
J16
J14
J9
H16
H14
G16
G14
G13
F16
L15
K12
K13
K16
J13
J11
J16
H15
H10
H12
G15
G10
G11
F16
A2/SA0
A3/SA1
A4/SA2
A5/SA3
A6/SA4
A7/SA5
A8/SA6
A9/SA7
A10/SA8
A11/SA9
A12/SA10
A13/SA11
A14/SA12
A15/SA13
Asynchronous Address Bus
Synchronous Address Bus
LOW
LOW
12 mA
O
F14
E16
A16/SB0
Async Address Bus
Sync Device Bank Address 0
Async Address Bus
Sync Device Bank Address 1
LOW
LOW
12 mA
O
E16
F13
A17/SB1
LOW
LOW
12 mA
O
E13
F11
D15
C16
B16
A15
A13
E14
D15
C16
C15
C14
B15
E11
A18
A19
A20
A21
A22
A23
A24
Asynchronous Address Bus
LOW
LOW
12 mA
O
G8
D8
A25/SCIO
Async Memory Address Bus
Smart Card Interface I/O (Data)
Async Memory Address Bus
Smart Card Interface Clock
Async Memory Address Bus
Smart Card Interface Reset
Async Memory Output Enable
Async Memory Write Byte Enable 0
Async Memory Write Byte Enable 3
Async Memory Chip Select 6
Sync Memory Clock Enable 1 or 2
Async Memory Chip Select 7
Sync Memory Clock Enable 0
Sync Memory Clock Enable 3
Sync Memory Clock
Sync Memory Chip Select 0
LOW: A25
LOW
12 mA
I/O
F8
B7
A26/SCCLK
LOW: A26
LOW
12 mA
I/O
A8
A7
A27/SCRST
LOW: A27
LOW
12 mA
O
D8
C8
D10
C8
F8
D9
nOE
nWE0
nWE3
HIGH
HIGH
HIGH
No Change
No Change
No Change
12 mA
12 mA
8 mA
O
O
O
B10
E9
CS6/SCKE1_2
LOW: CS6
No Change
12 mA
O
C10
A10
CS7/SCKE0
LOW: CS7
No Change
12 mA
O
G9
A10
C14
A11
B10
C13
SCKE3
SCLK
nSCS0
LOW
LOW
HIGH
LOW
12 mA
O
I/O
O
No Change
No Change
2
12 mA
Table 3. Functional Pin List (Cont’d)
BGA
PIN
LFBGA
PIN
SIGNAL
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
I/O NOTES
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