參數(shù)資料
型號: LH7A400N0F076B5
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學處理器
英文描述: 32-Bit System-on-Chip
封裝: LH7A400N0F000B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT1020-1.html<1<Always Pb-free,;LH7A400N0F076B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT
文件頁數(shù): 12/65頁
文件大小: 834K
代理商: LH7A400N0F076B5
LH7A400
32-Bit System-on-Chip
12
Rev. 01
16 July 2007
Preliminary data sheet
NXP Semiconductors
1. Signals beginning with ‘n’ are Active LOW.
2. The SCLK pin can source up to 12 mA and sink up to 20 mA. See ‘DC Characteristics’.
3. Schmitt trigger input; see ’DC Specifications’, page 31 for triggers points and hysteresis.
4. Input only for JTAG boundary scan mode.
5. Output only for JTAG boundary scan mode.
6. The internal pullup and pull-down resistance on all digital I/O pins is 50 k
7. When used as SMBCLK, this pin must have a resistor.
8. The RESET STATE is defined as the state during power-on reset.
9. The STANDBY STATE is defined as the state when the device is in standby. During this state,
I/O cells are forced to input (Input), output driving low (LOW), output driving high (HIGH), or their
current state is preserved (No Change). In some case, function selection has an overall effect on the standby state.
10.All unused USB Device pins with a differential pair must be pulled
to ground with a 15 k
resistor.
F6
F5
G1
G2
G4
G5
H1
H2
H3
G2
G1
H3
H5
H6
H7
H2
H1
J1
COL0
COL1
COL2
COL3
COL4
COL5
COL6
COL7
TBUZ
Keyboard Interface
HIGH
HIGH
8 mA
O
Timer Buzzer (254 kHz MAX.)
Boot Device Media Change. Used with WIDTH0
and WIDTH1 to specify boot memory device.
LOW
LOW
8 mA
O
C3
F5
MEDCHG
Input
No Change
I
3
P11
T14
WIDTH0
External Memory Width Pins. Also, used with
MEDCHG to specify the boot memory device size.
The pins must be pulled HIGH with a 33 k
resistor.
Input
No Change
I
3
R12
T15
WIDTH1
D1
D2
E3
F6
BATOK
nBATCHG
Battery OK
Battery Change
JTAG Data In. This signal is internally pulled-up t
o VDD.
JTAG Clock. This signal should be externally
pulled-up to VDD with a 33 k
resistor.
JTAG Data Out. This signal should be externally
pulled up to VDD with a 33 k
resistor.
JTAG Test Mode select. This signal is internally
pulled-up to VDD.
Test Pin 0. Internally pulled up to VDD. For Normal
mode, leave open. For JTAG mode, tie to GND.
See Table 4.
Test Pin 1. internally pulled up to VDD. For Normal
and JTAG mode, leave open. See Table 4.
Input
Input
No Change
No Change
I
I
3
3
A1
E5
TDI
Input
No Change
I
4
B1
C2
TCK
Input
No Change
I
3
B2
D3
TDO
High-Z
No Change
4 mA
O
C1
C1
TMS
Input
No Change
I
4
T12
P15
nTEST0
Input
No Change
I
4
R15
P13
nTEST1
Table 3. Functional Pin List (Cont’d)
BGA
PIN
LFBGA
PIN
SIGNAL
DESCRIPTION
RESET
STATE
STANDBY
STATE
OUTPUT
DRIVE
I/O NOTES
Table 4. nTest Pin Function
MODE
nTEST0
nTEST1
nURESET
JTAG
0
1
1
Normal
1
1
x
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