參數(shù)資料
型號(hào)： LC72151V
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30
封裝： SSOP-30
文件頁(yè)數(shù)： 8/29頁(yè)
文件大?。?/td> 326K
代理商： LC72151V
Structure of the DO Output Data (serial output data)
(3) OUT mode
No. 6976-16/29
LC72151V
C1
C2
C3
(2)
UNLOC
K
(1)
IN
-PORT
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
(3)
IF-CTR
C14
C15
C16
C17
C18
C19
UL
C0
0
* * * *
0
1
0
Address
1
0
1
DO
*: Bits that are set to 0.
DI
0
I1
*
I2
I3
I4
No.
Control block/data
Content
Related data
The bits I1 to I4 are set to the latched states of the I/O pins I/O-1 and I/O-2 and the input
pins HCTR/I-3 and LCTR/I-4. These states are latched at the point the IC enters data
output mode.
The pin states are latched regardless of the pin mode (input or output).
I1, I2
← I/O-1 and I/O-2 pin states
I3, I4
← HCTR/I-3 and LCTR/I-4 pin states
I/O-1
I/O-2
H/I-3
L/I-4
(1)
I/O port data
I4 to I1
Data created by latching the value for the unlock detection circuit
UL
← 0: Unlocked
1: Locked or in detection halt mode
UL0
UL1
(2)
PLL unlock data
UL
Data created by latching the value for the IF counter (20-bit binary counter)
C19
← MSB of the binary counter
C0
← LSB of the binary counter
CTE
GT0
GT1
(3)
IF counter binary counter
C19 to C0
Pin state =
high: 1
low: 0
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