參數(shù)資料
型號(hào)： LC72151V
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30
封裝： SSOP-30
文件頁(yè)數(shù)： 11/29頁(yè)
文件大?。?/td> 326K
代理商： LC72151V
Description of the High-Speed Locking Control System
The LC72151V realizes the maximum inter-band edge high-speed locking time 500 s by optimizing the filter constants
and internal status setting when the FMIN (high-speed mode) by setting DVS and SNS to 1. The following describes the
high-speed locking control system.
Procedure
The LC72151V operates as shown below when selecting FMIN (high-speed mode) and setting sub-charge pump
operation during unlocked.
Control Data
Setting data (CCB) necessary for the new high-speed locking control is described below.
This data is valid when the FMIN (high-speed mode) is selected by setting DVS and SNS to 1.
*: The recommended values are for reference purpose only, not the guarantee values for the fastest locking time.
No. 6976-19/29
LC72151V
Change value N
PDF/PDM1/PDM2/PDS/TGI1/TGI2 pin states
PDF
PDM1
*:
: operating;
: stopped (high-impedance)
PDM2
PDS
TGI1
TGI2
→
New high-speed locking control
(When the value N variation is under 16,
only operates the normal PLL.)
Stops the sub-charge pump and only the main-charge
pump operates. (Normal locking state)
Operates normal PLL when the local oscillation frequency
enters the high-speed locking frequency range.
(The sub-charge pump operates for the time set by the
high-speed locking completion flag output wait time.)
CCB data
Name (Selectable set value)
Description
Recommended value
The new high-speed locking control controls the convergence of the
target frequency into the set frequency range.
This data can be used to set the frequency range for convergence
judgement.
*: As the convergence range narrower, the locking time tends to be
shorter.
TLR0 = 0
TLR1 = 0
(±50 kHz)
TLR0/TLR1
High-speed locking convergence range
(±50/100/150/200 kHz)
During the new high-speed locking control, charge application from
the PDF pin and local oscillation frequency measurement for the
FMIN pin are repeatedly implemented.
This data can be used to set the Vt voltage stable time after the
charge is applied until the local oscillator frequency is measured.
*: Voltage stable time Vt changes according to the peripheral
circuit.
CWS0 = 1
CWS1 = 0
(5 s)
CWS0/CWS1
High-speed locking charge wait time
(0/2.5/5/10 s)
After the new high-speed locking control ends, since the phase
remains in convergence state in the internal unlock detection circuit
until the locking judgement is implemented, the sub-charge pump
will not operate by the sub-charge pump operation setting during
unlocked.
This data can be used to set the time to force the sub-charge pump
to operate for after the new high-speed locking control completes.
*: After the new high-speed locking control completes, the locking
time tends to be shortened by operating the sub-charge pump for
an adequate time.
HSE0 = 0
HSE1 = 1
(400 s)
HSE0/HSE1
High-speed locking completion flag output
wait time
(0/100/200/400 s)
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