參數(shù)資料
型號(hào)： LC72151V
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30
封裝： SSOP-30
文件頁(yè)數(shù)： 18/29頁(yè)
文件大?。?/td> 326K
代理商： LC72151V
(3) Notes on the IF counting using HCTR/I-3 and LCTR/I-4 pins
When counting the IF frequency, the application microcontroller must test the state of the IF IC SD (station detect)
signal, and only if the SD signal is present, turn on the IF counter buffer output and perform an IF count operation.
Methods in which auto-search operations are implemented only using the IF count may incorrectly stop at frequencies
where no station is present due to leakage from the IF counter buffer.
(4) Using the DO pin
At times other than data output mode, the DO pin can also be used to check for general-purpose counter count operation
completion, to output the unlock state detection signal, and to check for changes in the input pins.
Note that the states of the input pins (I/O-1 and I/O-2) can be directly input to the system microcontroller through the DO
pin.
(5) Power supply pins
Capacitors of at least 0.1 F must be inserted between the VDD and VSS power supply pins and between AVDD and AVSS
to reduce noise.
These capacitors must be located as close to the VDD and VSS, AVDD and AVSS pins as possible.
Additionally, power must be applied to AVDD before applying to VDD, and AVDD must be higher than or equal to VDD.
(6) Note on power application
After power is first applied, the power-on reset circuit initializes the IC. However, the CCB data RST must be set to 1 to
ensure the initialization.
(7) Notes on VCO design
The VCO must be designed so that the VCO oscillation does not stop if the control voltage (Vtune) becomes 0 V. If it is
possible for this oscillator to stop, use the charge pump control data (DLC) to forcible set Vtune to VCC temporarily to
prevent the PLL circuit from deadlocking. (This function is called a deadlock clear circuit.)
Pin states during a power-on reset
No. 6976-25/29
LC72151V
LC72151V
XO
State
Power-on state
F
I-1
F
O
I-2
O: Open
L: Low
F: Floating
State
Power-on state
UT
I/O-1
I/O-2
XBUF
O-3
VDD
VSS
FMIN
AMIN
HCTR/I-3
LCTR/I-4
AREF
AVDD
AVSS
AOUT1
XIN
CE
DI
CL
DO
AOUT2
AIN2
PDM2
PDF
PDM1
PDS
AIN1
TGI1
TGI2
TGO
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