參數(shù)資料
型號: LC72151V
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30
封裝: SSOP-30
文件頁數(shù): 20/29頁
文件大?。?/td> 326K
代理商: LC72151V
LC72151V State Setting Examples
1. In the case of FMRF 87.5 MHz reception (X’tal = 10.35 MHz/IF = +10.8 MHz)
FM VCO = 98.3 MHz
X’tal = 10.35 MHz, fref = 50 kHz
: XS = 1, R0 = R1 = R2 = R3 = 0
FMIN (high-speed mode) selected
: DVS = 1, SNS = 1
Dead-zone mode = DZD
: DZ0 = DZ1 = 1
Programmable divider divisor
98.3 MHz
÷ 50 kHz = 1966 → 07AE (Hex)
High-speed locking control conditions
High-speed locking convergence range = ±50 kHz
: TLR0 = TLR1 = 0
High-speed locking charge wait time = 5 s
: CWS0 = 1, CWS1 = 0
High-speed locking completion flag output wait time = 400 s : HSE0 = 0, HSE1 = 1
Unlock detection width = ±0.43 s
: UL0 = 0, UL1 = 1
No. 6976-27/29
LC72151V
P0
LSB
First Data IN1
Transmitted data
1
0
1
DI
8
0
00
0
10
1
101111000001101000000000000
2
P1
P2
P3
P4
P5
P6
P7
P8
P9
P1
0
P1
1
P1
2
P1
3
P1
4
P1
5
SN
S
DV
S
P
DC0
P
DC1
R0
R1
R2
R3
DT
0
DT
1
RS
T
CT
E
CT
S
0
CT
S
1
GT0
GT1
EA
7
0
B
0
MS B
I/O
-1
LSB
First Data IN2
1
DI
Address
9
1
00
0
*
0
0100010010000000010110000
2
I/O
*
-2
OUT1
OUT2
OUT3
XB
XS
TLR
0
TLR
1
CWS
0
CWS
1
HS
E
0
HS
E
1
H
/I-
3
L
/I-
4
CT
P
CT
C
IL
0
IL
1
ULD
UL0
UL1
DLC
DZ
0
DZ
1
TES
T
0
TES
T
1
TES
T
2
TES
T
3
01
9
0
D
0
MS B
[IN1]
[IN2]
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