- 您現(xiàn)在的位置：買賣IC網 > PDF目錄97997 > LC72151V PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30 PDF資料下載
參數(shù)資料
| 型號： | LC72151V |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO30 |
| 封裝： | SSOP-30 |
| 文件頁數(shù)： | 6/29頁 |
| 文件大小： | 326K |
| 代理商： | LC72151V |
第1頁第2頁第3頁第4頁第5頁當前第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
No. 6976-14/29
LC72151V
Continued from preceding page.
No.
Control block/data
Content
Related data
Width selection for the phase error (E) detection function used to determine the PLL
locked/unlocked state. When a phase error greater than the E detection width from the
table occurs, the PLL circuit is seen as in the unlocked state.
*: When unlocked, the DO pin goes low and the serial data output is UL = 0.
ULD
DT0, DT1
DVS
SNS
(9)
Unlock state detection data
UL0, UL1
Controls the phase comparator dead band.
*: The phase comparator operates in DZA mode after the power-on reset. (Recomended
modes: DZD, DZC)
(11)
Phase comparator control data
DZ0, DZ1
Bit that forcible sets the charge pump output to the low level.
DLC = 1: Low level
DLC = 0: Normal operation
*: If a deadlock occurs due to the VCO control voltage (Vtune) going to zero and stopping
the VCO oscillator, set the charge pump output to the low level and set Vtune to VCC to
escape from the deadlocked state (deadlock clearing circuit). Normal operation is
selected after the power-on reset.
(10)
Charge pump control data
DLC
Data to control the frequency in the convergence range to judge the high-speed locking
control completion. This data is valid when FMIN (high-speed mode) is selected by
setting DVS and SNS to 1.
*:The convergence range is 200 kHz at a power-on reset.
Refer to Description of the High-Speed Locking Control System (P.19) for details.
(12)
High-speed locking convergence
range control data
TLR0, TLR1
UL1
UL0
E detection width
Detection output
X’tal
0
Stopped
Open
10.25 M/10.35 MHz
0
1
0
Directly outputs E
10.25 M/10.35 MHz
±0.49 s
E is extended by
10.25 MHz
0.1 to 0.2 ms.
1
0
±0.49 s
E is extended by
10.35 MHz
0.11 to 0.22 ms.
(fr = 30/9/3 k)
±0.43 s
E is extended by
10.35 MHz (Other
0.1 to 0.2 ms.
than fr = 30/9/3 k)
±0.98 s
E is extended by
10.25 MHz
0.1 to 0.2 ms.
1
±0.97 s
E is extended by
10.35 MHz
0.11 to 0.22 ms.
(fr = 30/9/3 k)
±0.87 s
E is extended by
10.35 MHz (Other
0.1 to 0.2 ms.
than fr = 30/9/3 k)
0.1 to 0.22ms
E
DO
Extended
Unlock state output
DZ1
DZ0
Dead band mode
0
DZA
0
1
DZB
1
0
DZC
1
DZD
TLR1 TLR0
Convergence range [kHz]
0
50
0
1
100
1
0
150
1
200
Continued on next page.
相關PDF資料 |
PDF描述 |
|---|---|
| LC7216M | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| LCP-10G3A4EDR | FIBER OPTIC TRANSCEIVER, 840-860nm, 10312.5Mbps(Tx), 10312.5Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
| LCP-10G3A4EDRH | FIBER OPTIC TRANSCEIVER, 840-860nm, 10312.5Mbps(Tx), 10312.5Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
| LCP-10G3B4QDR | FIBER OPTIC TRANSCEIVER, 1260-1355nm, 10000Mbps(Tx), 10000Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
| LCP-10G3B4QDRT | FIBER OPTIC TRANSCEIVER, 1260-1355nm, 10000Mbps(Tx), 10000Mbps(Rx), SURFACE MOUNT, LC CONNECTOR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LC72151VS-MPB-E | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Ammo Pack |
| LC72151VS-TRM-E | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LC7215F | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:MW/LW PLL Frequency Synthesizers |
| LC7215FM | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:MW/LW PLL Frequency Synthesizers |
| LC7216M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
發(fā)布緊急采購，3分鐘左右您將得到回復。