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參數(shù)資料
| 型號(hào)： | L64118 |
| 廠(chǎng)商： | LSI CORP |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁(yè)數(shù)： | 3/68頁(yè) |
| 文件大?。?/td> | 877K |
| 代理商： | L64118 |
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L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 11
SDRAM controller module. The block includes a PID processor unit
(PPU) that is compliant with DVB and JSAT and meets the requirements
of many other service providers, including Canal+, SkyPerfect, and
BSkyB.
The unit can process up to 32 PIDs simultaneously. It provides extensive
ltering of PSI, SI, and Private Sections. The PSI, SI, and Private
Sections are ltered according to 32 user-programmable match/mask
PIDs. Section data that passes ltering is stored in cyclic buffers (in off-
chip memory) associated with each PID. Each section in each PID can
be ltered against 32 lters. (Every section undergoes a CRC32 check.
An enable bit controls the CRC checking of all section types.) The on-
chip descrambler unit increases system security. The audio and video
data are reduced to PES streams and delivered to the A/V decoder.
SDRAM Controller
The SDRAM controller and resource arbitration logic makes efcient use
of SDRAM bandwidth. This chip’s low-cost system implementation
approach dictates usage of the external SDRAM for both transport and
general system functions. The L64118 supports various SDRAM
congurations using 16 Mbit and 64 Mbit devices, for a total memory size
of 2, 8, or 16 Mbytes of external SDRAM.
The SDRAM controller arbitrates access to the external SDRAM. This
logic provides the maximum possible SDRAM bandwidth to the on-chip
CPU without increasing the need for buffers or other resources.
External System Bus (EBus)
The External System Bus is a general-purpose 16- and 32-bit system
bus used for communication with external components in the system.
This bus provides the system designer with an interface that permits the
glueless connection of devices like FLASH, ROMs, and external
peripherals.
The EBus comprises a 32-bit wide interface with multiplexed address and
data. Eight address bits are available as demultiplexed bits for easy
interface to devices that do not need the full address space. In addition
a demultiplexed mode can be congured to provide a 24-bit address and
16-bit data bus.
118bds Page 11 Wednesday, February 3, 1999 12:37 PM
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| L64133-10GC | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:Arithmetic Processor |
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