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參數(shù)資料
| 型號： | L64118 |
| 廠商： | LSI CORP |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封裝： | PLASTIC, BGA-256 |
| 文件頁數(shù)： | 27/68頁 |
| 文件大?。?/td> | 877K |
| 代理商： | L64118 |
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L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 33
Transmit Data - Serial ICEPort
Output
If GPIO[43] is sampled LOW during reset, this pin serves
as ICE_TX, the serial ICE transmit data output port. By
default, this signal is not asserted after reset.
TXD2
Transmit Data Port 2
Output
This signal outputs data in compliance with the RS232
protocol’s asynchronous specication. The data rate on
this pin is determined by programming the SIO Baud
Rate register. Data transmitted on TXD2 comes from the
Transmit register of Port 2. By default, this signal is not
asserted after reset.
SDRAM Interface
The following group of signals provides the interface between the L64118
and external SDRAM devices. The SDRAM interface works with
PC66/100 compliant SDRAMs. The L64118 SDRAM interface runs at 54
MHz and is capable of accessing 2, 4, 8, or 16 Mbyte memory
congurations using 16 Mbit or 64 Mbit devices.
This interface has a 16-bit data bus (SBD[15:0]). The upper and lower
byte mask signals (SDQMH and SDQML) control halfword and byte
accesses. The SBA[1:0] outputs support two- and four-bank SDRAM
devices. The L64118 automatically performs SDRAM refreshes.
The L64118 does not support the Chip Select (CSn) and Clock Enable
(CKE) signals. Tie these SDRAM signals active LOW and HIGH,
respectively, on the SDRAM device(s) used.
SA[11:0]
SDRAM Address Bus
Output
These signals carry the 12-bit SDRAM address bus. The
number of row and column address bits used is
programmable in the SDRAM Conguration register.
SBA[1:0]
SDRAM Bank Select
Output
These signals allow access to SDRAM devices with
either two or four banks. The number of bank select bits
used is programmable in the SDRAM Conguration
register.
118bds Page 33 Wednesday, February 3, 1999 12:37 PM
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