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L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
The protocol of this pin is similar to that of TxD1. The
receive baud rate is determined by programming the
SIO Baud Rate register. The data received on RXD1 is
latched in the Receive register of Port 1. If GPIO[43] is
sampled LOW during reset, then this pin serves as the
receive port for the ICEport in the L64118.
Receive Data - Serial ICE Port
Input
When the serial ICE mode is enabled, this pin functions
as ICE_RX, the receive data port input.
RXD2
Receive Data Port 2
Input
This signal provides serial data from an external RS232
device. The protocol of this pin is similar to that of TxD2.
The receive baud rate is determined by programming the
SIO Baud Rate register. The data received on RXD2 is
latched in the Receive register of Port 2.
TCLK
Transmit Serial Data Clock
Input
This signal is used for the transmit clock in the enhanced
UART mode.
TXD0
Transmit Data Port 0
Output
This signal outputs data in compliance with the RS232
protocol’s asynchronous specication. The transmit baud
rate is determined by programming the SIO Baud Rate
register. Data transmitted on TXD0 comes from the
Transmit register of Port 0. By default, this signal is not
asserted after reset.
TXD1/ICE_TX
Transmit Data Port 1
Output
This pin can serve as either the Transmit Data port signal
of SIO1, or as the ICEport receive input for the ICEport
module. The strap option on GPIO[43] controls this pin’s
functionality and usage. If GPIO[43] is sampled HIGH
during reset, this pin serves as TXD1.
When set to TXD1, this signal outputs data in compliance
with the RS232 protocol’s asynchronous specication.
The data rate on this pin is determined by programming
the SIO Baud Rate register. Data transmitted on TXD1
comes from the Transmit register of Port 1.
118bds Page 32 Wednesday, February 3, 1999 12:37 PM