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Display Areas
9-5
9.3 Display Areas
From the Display Controller point of view, the entire display area can best
be described as a blank area that is bounded vertically by the vertical
sync (VS) input and horizontally by the horizontal sync (HS) input. The
HS and VS input pulses determine field and line timing. For reliable
operation, the sync inputs must be synchronous to the 27-MHz device
clock. Additionally, VS must be received every field time and HS must be
received every line time.
The Display Controller times and locates several display areas within the
entire display area. Refer to
Figure 9.2
. The areas include the active
display area, the main display area, and the OSD area. The bottom-most
layer is black. The active display area resides just above the black layer.
The main display area is contained within the active display area. The
OSD display is mixed on top of the main area.
Table 9.2
Television Standard Select Default Values
Parameter
Register[Bits]
NTSC
PAL
Page Ref.
Main Reads Per Line[6:0]
278[6:0]
90
90
4-65
Vline Count Init[2:0]
282[2:0]
4
1
4-66
Pixel State Reset Value [1:0]
284[4:3]
2
2
4-67
Main Start Row[10:0]
299[2:0], 297[7:0]
23
23
4-70
Main End Row[10:0]
299[6:4], 298[7:0]
262
310
Main Start Column[10:0]
302[2:0], 300[7:0]
244
264
4-70
Main End Column[10:0]
302[6:4], 301[7:0]
1683
1703
SAV Start Col[10:0]
308[2:0], 306[7:0]
240
260
4-72
EAV Start Co[10:0]l
308[6:4], 307[7:0]
1684
1704
Vcode Zero[4:0]
303[4:0]
21
21
4-70
Vcode Even[8:0]
303 bit 5, 304[7:0]
262
310
4-71
Vcode Even Plus 1
303 bit 6
1
0
4-70
Fcode[8:0]
303 bit 8, 305[7:0]
265
312
4-71